DS80PCI402_15 Datasheet, PDF (4/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
www.ti.com
Pin Functions^(1)(2)(3)(4)
PIN
NAME
I/O, TYPE
NUMBER
DESCRIPTION
DIFFERENTIAL HIGH SPEED I/Os
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-
1, 2, 3, 4,
5, 6, 7, 8
I
Inverting and non-inverting 50-Ω driver bank B outputs with de-emphasis. Compatible
with AC-coupled CML inputs.
INA_0+, INA_0-,
INA_1+, INA_1-,
INA_2+, INA_2-,
INA_3+, INA_3-
10, 11, 12,
13, 15, 16,
17, 18
I
Inverting and non-inverting differential inputs to bank A equalizer. A gated on-chip 50-Ω
termination resistor connects INA_n+ to VDD and INA_n- to VDD depending on the state
of RXDET. See Table 4
AC coupling required on high-speed I/O
INB_0+, INB_0-,
INB_1+, INB_1-,
INB_2+, INB_2-,
INB_3+, INB_3-
45, 44, 43,
42, 40, 39,
38, 37
Inverting and non-inverting differential inputs to bank B equalizer. A gated on-chip 50-Ω
O
termination resistor connects INB_n+ to VDD and INB_n- to VDD depending on the state
of RXDET. See Table 4
AC coupling required on high-speed I/O
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
35, 34, 33,
32, 31, 30,
29, 28
O
Inverting and non-inverting 50-Ω driver bank A outputs with de-emphasis. Compatible
with AC-coupled CML inputs.
CONTROL PINS — SHARED (LVCMOS)
ENSMB
System management bus (SMBus) enable pin
48
I, 4-LEVEL,
LVCMOS
Tie 1 kΩ to VDD (2.5-V mode) or VIN (3.3-V mode) = Register access SMBus slave
mode
FLOAT = Read external EEPROM (master SMBUS mode)
Tie 1 kΩ to GND = Pin mode
ENSMB = 1 (SMBus SLAVE MODE)
SCL
50
I, 2-LEVEL,
LVCMOS,
O, open
drain
In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or open drain output.
External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus
interface standards⁽⁵⁾
SDA
49
I, 2-LEVEL,
LVCMOS,
O, open
drain
In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.
External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus
interface standards⁽⁵⁾
AD0-AD3
54, 53, 47,
46
I, 4-LEVEL,
LVCMOS
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the user set SMBus
slave address inputs.
External 1-kΩ pullup or pulldown recommended.
READ_EN / SD_TH 26
I, FLOAT In SMBus Slave Mode, this pin is not used. Leave it floating.
ENSMB = FLOAT (SMBus MASTER MODE)
I, 2-LEVEL, Clock output when loading EEPROM configuration, reverting to SMBus clock input when
SCL
50
LVCMOS, EEPROM load is complete (ALL_DONE = 0).
O, open External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus
drain
interface standards⁽⁵⁾
SDA
49
I, 2-LEVEL,
LVCMOS,
O, open
drain
In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.
External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus
interface standards⁽⁵⁾
AD0-AD3
READ_EN
54, 53, 47,
46
26
I, 4-LEVEL,
LVCMOS
I, 2-LEVEL,
LVCMOS
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the user set SMBus
slave address inputs.
External 1-kΩ pullup or pulldown recommended.
A logic low on this pin starts the load from the external EEPROM⁽⁶⁾
Once EEPROM load is complete (ALL_DONE = 0), this pin functionality remains as
READ_EN. It does not revert to an SD_TH input.
(1) LVCMOS inputs without the “FLOAT” conditions must be driven to a logic low or high at all times or operation is not verified.
(2) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10% to 90%.
(3) For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
(4) For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
(5) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5-V mode or 3.3-V mode.
(6) When READ_EN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to
an invalid or blank hex file, the DS80PCI402 waits indefinitely in an unknown state where SMBus access is not possible. ALL_DONE pin
remains high in this situation.
4
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