DS80PCI402_15 Datasheet, PDF (41/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

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DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
Table 11. Suggested Device Settings in SMBus Slave Mode (continued)
WRITE VALUE
0x00
0xAD
0x00
COMMENTS
Set CHA_3 EQ to 0x00.
Set CHA_3 VOD to 101'b (1.2 Vp-p).
Set CHA_3 DEM to 000'b (0 dB).
9.2 Typical Application
The DS80PCI402 extends PCB trace and cable reach in PCIe Gen1, 2 and 3 applications by applying
equalization to compensate for the insertion loss of the trace or cable. In Gen 3 mode, the device aids
specifically in the equalization link training to improve the margin and overall eye inside the Rx. The DS80PCI402
can be used on the motherboard, mid plane (riser card), end-point target cards, and active cable assemblies.
The capability of the DS80PCI402 performance is shown in the following two test setup connections.
Pattern
Generator
V_ID = 1.0 Vp-p,
DE = 0 dB
8 Gb/s, PRBS23
TL
Lossy Channel
IN DS80PCI402 OUT
Figure 8. Test Setup Connections Diagram
Scope
BW = 50 GHz
Pattern
Generator
V_ID = 1.0 Vp-p,
DE = -9 dB
8 Gb/s, PRBS23
TL1
Lossy Channel
IN DS80PCI402 OUT
TL2
Lossy Channel
Figure 9. Test Setup Connections Diagram
Scope
BW = 50 GHz
9.2.1 Design Requirements
As with any high speed design, there are many factors which influence the overall performance. The following list
indicates critical areas for consideration during design.
• Use 100-Ω impedance traces. Length matching on the P and N traces should be done on the single-end
segments of the differential pair.
• Use uniform trace width and trace spacing for differential pairs.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• For Gen3, AC-coupling capacitors of 220 nF are recommended, maximum body size is 0402, and add cutout
void on GND plane below the landing pad of the capacitor to reduce parasitic capacitance to GND.
• Back-drill connector vias and signal vias to minimize stub length.
• Use Reference plane vias to ensure a low inductance path for the return current.
9.2.2 Detailed Design Procedure
The DS80PCI402 should be placed at an offset location and close to the Rx with respect to the overall channel
attenuation. The suggested settings are recommended as a starting point for most applications. Once these
settings are configured, additional adjustments of the DS80PCI402 EQ or DE may be required to optimize the
repeater performance. The CTLE and DFE coefficient in the Rx can also be adjusted to further improve the eye
opening.
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Product Folder Links: DS80PCI402
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