DS80PCI402_15 Datasheet, PDF (36/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
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Address Register Name
0x35
CH5 - CHA_1
DEM
0x36
CH5 - CHA_1
IDLE Threshold
0x37
0x38
0x39
Reserved
Reserved
CH6 - CHA_2
IDLE, RXDET
0x3A
CH6 - CHA_2
EQ
Table 9. SMBus Slave Mode Register Map (continued)
Bit Field
Type Default
EEPROM Description
Bit
7
RXDET
STATUS
R 0x02
Observation bit for RXDET CH5 - CHA_1
1: RX = detected
0: RX = not detected
6:5 RATE_DET
R
STATUS
Observation bit for RATE_DET CH5 - CHA_1
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved
R/W
Set bits to 0
2:0 DEM Control R/W
Yes
OUTA_1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
7
Reserved
R/W 0x00
Yes
Set bit to 0
6:4 Reserved
Set bits to 0
3:2 IDLE tha
Yes
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd
Yes
Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
7:0 Reserved
R/W 0x00
Set bits to 0
7:0 Reserved
R/W 0x00
Set bits to 0
7:6 Reserved
R/W 0x00
Set bits to 0
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET
Yes
00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is hi-Z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-Z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved
Set bits to 0
7:0 EQ Control
R/W 0x2F
Yes
INA_2 EQ Control - total of 256 levels
See Table 2
36
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