DS80PCI402_15 Datasheet, PDF (17/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

www.ti.com
DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
Programming (continued)
Table 6. Device Slave Address Bytes
AD[3:0] SETTINGS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADDRESS BYTES (HEX)
B0
B2
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
7-BIT SLAVE ADDRESS (HEX)
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
The SDA/SCL pins are 3.3 V tolerant, but are not 5 V tolerant. An external pullup resistor is required on the SDA
and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.
8.5.2 Transfer of Data Through the SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A high-to-low transition on SDA while SCL is High indicates a message START condition.
STOP: A low-to-high transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.
8.5.3 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: DS80PCI402
Submit Documentation Feedback
17