DS80PCI402_15 Datasheet, PDF (28/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
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Address Register Name
0x08
Override
Pin Control
0x09
0x0A
Reserved
Signal Detect
Monitor
0x0B
0x0C
0x0D
0x0E
Reserved
Reserved
Reserved
CH0 - CHB_0
IDLE, RXDET
0x0F
CH0 - CHB_0
EQ
Table 9. SMBus Slave Mode Register Map (continued)
Bit Field
Type Default
EEPROM Description
Bit
7
Reserved
R/W 0x00
Set bit to 0
6
Override SD_TH
Yes
1: Block SD_TH pin control
0: Allow SD_TH pin control
5
Reserved
Yes
Set bit to 0
4
Override IDLE
Yes
1: IDLE control by registers
0: IDLE control by signal detect
3
Override
RXDET
Yes
1: Block RXDET pin control
0: Allow RXDET pin control
2
Override RATE
Yes
1: Block RATE pin control
0: Allow RATE pin control
1:0 Reserved
Set bits to 0
7:0 Reserved
R/W 0x00
Set bits to 0
7:0 SD_TH Status R 0x00
CH7 - CH0 Internal Signal Detector Indicator
[7]: CH7 - CHA_3
[6]: CH6 - CHA_2
[5]: CH5 - CHA_1
[4]: CH4 - CHA_0
[3]: CH3 - CHB_3
[2]: CH2 - CHB_2
[1]: CH1 - CHB_1
[0]: CH0 - CHB_0
0 = Signal detected at input (active data)
1 = Signal not detected at input (idle state)
NOTE: These bits only function when RATE pin
= FLOAT.
7
Reserved
R/W 0x00
Set bits to 0
6:0 Reserved
R/W 0x70
Yes
Set bits to 111 0000'b
7:0 Reserved
R/W 0x00
Set bits to 0
7:0 Reserved
R/W 0x00
Set bits to 0
7:6 Reserved
R/W 0x00
Set bits to 0
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET
Yes
00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is hi-Z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-Z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved
Set bits to 0
7:0 EQ Control
R/W 0x2F
Yes
INB_0 EQ Control - total of 256 levels
See Table 2
28
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