DS80PCI402_15 Datasheet, PDF (16/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
SD_TH
0
R
F (default)
1
Table 5. Signal Detect Threshold Level⁽¹⁾
SMBus REG BIT [3:2] AND [1:0]
10
01
00
11
ASSERT LEVEL (TYP)
210 mVp-p
160 mVp-p
180 mVp-p
190 mVp-p
(1) VDD = 2.5 V, 25° C, and 0101 pattern at 8 Gbps.
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DEASSERT LEVEL (TYP)
150 mVp-p
100 mVp-p
110 mVp-p
130 mVp-p
8.4 Device Functional Modes
The DS80PCI402 is a low-power 8-channel repeater optimized for PCI Express Gen 1/2 and 3. The DS80PCI402
compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The DS80PCI402 operates in
three modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode
(ENSMB = float) to load register information from external EEPROM; refer to SMBus Master Mode for additional
information.
8.4.1 Pin Control Mode
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side
independently. When de-emphasis is asserted VOD is automatically adjusted per the De- Emphasis table below.
The RXDET pins provides automatic and manual control for input termination (50 Ω or > 50 kΩ). RATE setting is
also pin controllable with pin selections (Gen 1/2, auto detect and Gen 3). The receiver electrical idle detect
threshold is also adjustable via the SD_TH pin.
8.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx
and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (RATE,
RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit
is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is
driven low all registers are reset to their default state. If PRSNT is asserted while ENSMB is high, the registers
retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 256 possible equalization settings. The 4-Level Input Configuration Guidelines
show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-
Emphasis levels are set by registers.
8.5 Programming
8.5.1 System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ
to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS80PCI402 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address
inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS80PCI402 has a 7-bit slave address.
The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the
AD[3:0] inputs. Below are the 16 addresses.
16
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