DS80PCI402_15 Datasheet, PDF (19/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

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DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
The following example represents a 2 kbits (256 × 8-bit) EEPROM in hex format for the DS80PCI402 device. The
first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all
devices connected to the SMBus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled,
a fixed pattern (0xA5) is written/read instead of the CRC byte from the CRC location, to simplify the control.
There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the
EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS80PCI402
address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly
address the EEPROM. There are 37 bytes of data size for each DS80PCI402 device.
:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
For more information in regards to EEPROM programming and the hex format, see SNLA228.
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Product Folder Links: DS80PCI402
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