DS80PCI402_15 Datasheet, PDF (30/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
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Address Register Name
0x15
CH1 - CHB_1
IDLE, RXDET
0x16
0x17
CH1 - CHB_1
EQ
CH1 - CHB_1
VOD
0x18
CH1 - CHB_1
DEM
Table 9. SMBus Slave Mode Register Map (continued)
Bit Field
Type Default
EEPROM Description
Bit
7:6 Reserved
R/W 0x00
Set bits to 0
5
IDLE_AUTO
Yes
1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4
IDLE_SEL
Yes
1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET
Yes
00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times)
then stops; termination is hi-Z until detection;
once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is hi-Z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved
Set bits to 0.
7:0 EQ Control
R/W 0x2F
Yes
INB_1 EQ Control - total of 256 levels.
See Table 2
7
Short Circuit
R/W 0xAD
Yes
Protection
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
Yes
1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved
Yes
Set bits to default value - 101
2:0 VOD Control
Yes
OUTB_1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
7
RXDET
STATUS
R 0x02
Observation bit for RXDET CH1 - CHB_1
1: RX = detected
0: RX = not detected
6:5 RATE_DET
R
STATUS
Observation bit for RATE_DET CH1 - CHB_1
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved
R/W
Set bits to 0
2:0 DEM Control R/W
Yes
OUTB_1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
30
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