DS80PCI402_15 Datasheet, PDF (22/54 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 4-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI402
SNLS324E – APRIL 2011 – REVISED JANUARY 2015
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Table 7. EEPROM Register Map - Single Device with Default Value (continued)
EEPROM Address Byte
Description
SMBus Register _0x10
Default
Value
0xAD
Bit 7
ch2_Sel_scp
0x1E[7]
1
Bit 6
ch2_Sel_mode
0x1E[6]
0
Bit 5
ch2_RES_2
0x1E[5]
1
Bit 4
ch2_RES_1
0x1E[4]
0
Bit 3
ch2_RES_0
0x1E[3]
1
Bit 2
ch2_VOD_2
0x1E[2]
1
Bit 1
ch2_VOD_1
0x1E[1]
0
BIt 0
ch2_VOD_0
0x1E[0]
1
Description
SMBus Register
Default
Value
0x40
0x11
ch2_DEM_2
0x1F[2]
0
ch2_DEM_1
0x1F[1]
1
ch2_DEM_0
0x1F[0]
0
ch2_Slow
0x20[7]
0
ch2_idle_tha_1
0x20[3]
0
ch2_idle_tha_0
0x20[2]
0
ch2_idle_thd_1
0x20[1]
0
ch2_idle_thd_0
0x20[0]
0
Description
SMBus Register
Default
Value
0x02
0x12
ch3_Idle_auto
0x23[5]
0
ch3_Idle_sel
0x23[4]
0
ch3_RXDET_1
0x23[3]
0
ch3_RXDET_0
0x23[2]
0
ch3_BST_7
0x24[7]
0
ch3_BST_6
0x24[6]
0
ch3_BST_5
0x24[5]
1
ch3_BST_4
0x24[4]
0
Description
SMBus Register
Default
Value
0xFA
0x13
ch3_BST_3
0x24[3]
1
ch3_BST_2
0x24[2]
1
ch3_BST_1
0x24[1]
1
ch3_BST_0
0x24[0]
1
ch3_Sel_scp
0x25[7]
1
ch3_Sel_mode
0x25[6]
0
ch3_RES_2
0x25[5]
1
ch3_RES_1
0x25[4]
0
Description
SMBus Register
Default
Value
0xD4
0x14
ch3_RES_0
0x25[3]
1
ch3_VOD_2
0x25[2]
1
ch3_VOD_1
0x25[1]
0
ch3_VOD_0
0x25[0]
1
ch3_DEM_2
0x26[2]
0
ch3_DEM_1
0x26[1]
1
ch3_DEM_0
0x26[0]
0
ch3_Slow
0x27[7]
0
Description
SMBus Register
Default
Value
0x09
0x15
ch3_idle_tha_1
0x27[3]
0
ch3_idle_tha_0
0x27[2]
0
ch3_idle_thd_1
0x27[1]
0
ch3_idle_thd_0
0x27[0]
0
ovrd_fast_idle
0x28[6]
0
en_high_idle_th_n en_high_idle_th_s en_fast_idle_n
0x28[5]
0x28[4]
0x28[3]
0
0
1
Description
SMBus Register
Default
Value
0x80
0x16
en_fast_idle_s
0x28[2]
1
eqsd_mgain_n
0x28[1]
0
eqsd_mgain_s
0x28[0]
0
ch4_Idle_auto
0x2B[5]
0
ch4_Idle_sel
0x2B[4]
0
ch4_RXDET_1
0x2B[3]
0
ch4_RXDET_0
0x2B[2]
0
ch4_BST_7
0x2C[7]
0
Description
SMBus Register
Default
Value
0x5F
0x17
ch4_BST_6
0x2C[6]
0
ch4_BST_5
0x2C[5]
1
ch4_BST_4
0x2C[4]
0
ch4_BST_3
0x2C[3]
1
ch4_BST_2
0x2C[2]
1
ch4_BST_1
0x2C[1]
1
ch4_BST_0
0x2C[0]
1
ch4_Sel_scp
0x2D[7]
1
22
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