TL16C552 Datasheet, PDF (9/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

Data Bus
Address Bus
Control Bus
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw1
CLK (XTAL1)
2V
0.8 V
tw2
fclock = 8 MHz MAX
Figure 1. Clock Input (CLK) Voltage Waveform
Device Under Test
TL16C552
2.54 V
680 Ω
82 pF†
†Includes _{scope and jig capacitance}
Figure 2. Output Load Circuit
TL16C552
Serial
Channel 1
Buffers
Option
Jumpers
Dual
Ace and
Printer
Port
Serial
Channel 2
Buffers
Parallel
Port
R/C
Network
Figure 3. Basic Test Configuration
9-Pin D Connector
9-Pin D Connector
25-Pin D Connector
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