TL16C552 Datasheet, PDF (13/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SIN
Sample
CLK
Time Out or
Trigger Level
Interrupt
LSI
Interrupt
IOR
(RD LSR)
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Stop
td9
(see Note A)
50 %
50 %
50 %
td9
Top Byte of FIFO 50 %
tpd6
Active
50 %
tpd6
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOR
(RD RBR)
Active
50 %
50 %
Active
Previous Byte
Read From FIFO
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
IOR
(RD RBR)
SIN
(first byte)
Stop
50 %
Active
See Note A
Sample
CLK
RXRDY
td9
(see Note B )
50 %
tpd7
Figure 12. Receiver Ready Mode 0 Waveforms
NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCR0=1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.
50 %
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