TL16C552 Datasheet, PDF (29/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Reading the MSR register clears the delta modem status indications but has no affect on the other status bits.
For LSR and MSR, the setting of status bits is inhibited during status register read operations. When a status
condition is generated during a read IOR operation, the status bit is not set until the trailing edge of the read.
If a status bit is set during a read operation, and the same status condition occurs, that status bit is cleared at
the trailing edge of the read instead of being set again. In the loop back mode, when modem status interrupts
are enabled, the CTS, DSR, RI and DCD input terminals are ignored. However, a modem status interrupt can
still be generated by writing to MCR3 – MCR0. Applications software should not write to the MSR.
parallel port registers
The TL16C552 parallel port can interface to the device to a Centronics-style printer interface. When chip select
2 (CS2) is low, the parallel port is selected. Table 12 shows the registers associated with this parallel port. The
read or write function of the register is controlled by the state of the read (IOR) and write (IOW) terminal as
shown. The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of the printer in the six most significant
bits. The status bits are printer busy BSY, acknowledge (ACK) which is a handshake function, paper empty (PE),
printer selected (SLCT), error (ERR) and printer interrupt (PRINT). The read control register allows the state
of the control lines to be read. The write control register sets the state of the control lines. They are direction
(DIR), interrupt enable (INT2 EN), select in (SLIN), initialize the printer (INIT), autofeed the paper (AFD), and
strobe (STB), which informs the printer of the presence of a valid byte on the parallel bus. The write data register
allows the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the
parallel port implementation used in the IBM™ serial parallel adaptor.
REGISTER
Read Data
Read Status
Read Control
Write Data
Write Control
BIT 7
PD7
BSY
0
PD7
0
Table 12. Parallel Port Registers
BIT 6
PD6
ACK
0
PD6
0
BIT 5
PD5
PE
DIR
PD5
DIR
REGISTER BITS
BIT 4
BIT 3
PD4
PD3
SLCT
ERR
INT2 EN SLIN
PD4
PD3
INT2 EN SLIN
BIT 2
PD2
PRINT
INIT
PD2
INIT
BIT 1
PD1
1
AFD
PD1
AFD
BIT 0
PD0
1
STB
PD0
STB
Table 13. Parallel Port Register Select
CONTROL TERMINALS
IOR
IOW
CS2
A1
L
H
L
L
L
H
L
L
L
H
L
H
L
H
L
H
H
L
L
L
H
L
L
L
H
L
L
H
H
L
L
H
REGISTER SELECTED
A0
L
Read data
H
Read status
L
Read control
H
Invalid
L
Write data
H
Invalid
L
Write control
H
Invalid
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