TL16C552 Datasheet, PDF (2/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
description (continued)
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
between 1 and (2¹⁶ – 1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.
functional block diagram
28
CTS0
31
DSR0
29
DCD0
RI0 ³⁰
SIN0 ⁴¹
CS0 ³²
14 – 21
DB – DB7
CTS1 ¹³
DSR1 ⁵
DCD1 ⁸
RI1 ⁶
SIN1 ⁶²
CS1 ³
8
8
ACE
#1
ACE
#2
24
RTS0
25
DTR0
26
SOUT0
45 _INT0
9 _RXRDY0
22 _TXRDY0
12 _RTS1
11 _DTR1
10 _SOUT1
60 _INT1
61 _RXRDY1
42 _TXRDY1
A0 – A2
IOW
IOR
RESET
CLK
35 – 33
36
37
39
4
Select
and
Control
Logic
8
63
ERR
65
SLCT
66
BUSY
PE ⁶⁷
ACK ⁶⁸
PEMD ¹
CS2 ³⁸
ENIRQ ⁴³
Parallel
Port
44
BDO
8 _{53 – 46 PD0 – PD7}
57 _INIT
56 _AFD
55 _STB
58 _SLIN
59 _INT2
2
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