TL16C552 Datasheet, PDF (17/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
ADDRESS
0
REGISTER
MNEMONIC
RBR
(read only)
0
THR
(write only)
0†
DLL
1†
DLM
1
IER
BIT 7
Data
Bit 7
(MSB)
Data
Bit 7
Bit 7
Bit 15
0
BIT 6
Data
Bit 6
Data
Bit 6
Bit 6
Bit 14
0
2
FCR
Receiver
Receiver
(write only)
Trigger
Trigger
(MSB)
(LSB)
2
IIR
FIFOs
FIFOs
(read only)
Enabled‡
Enabled‡
3
LCR
(DLAB)
Set
Divisor latch
break
access bit
4
MCR
0
0
5
LSR
Error in
(TEMT)
receiver
FIFO‡
Transmitter
empty
6
MSR
(DCD)
(RI)
Data carrier
Ring
detect
indicator
7
SCR
Bit 7
Bit 6
† _{DLAB = 1}
‡ _{These bits are always 0 when FIFOs are disabled.}
BIT 5
Data
Bit 5
Data
Bit 5
Bit 5
Bit 13
0
Reserved
0
Stick
parity
0
(THRE)
Transmitter
holding
register
empty
(DSR)
Data set
ready
Bit 5
REGISTER BIT NUMBER
BIT 4
BIT 3
Data
Bit 4
Data
Bit 3
Data
Bit 4
Bit 4
Bit 12
0
Data
Bit 3
Bit 3
Bit 11
(EDSSI)
Enable
modem
status
interrupt
Reserved
0
DMA
mode
select
Interrupt ID
Bit (2)‡
(EPS)
Even parity
select
Loop
(BI)
Break
interrupt
(PEN)
Parity
enable
Enable
external
interrupt
(INT0 or
INT1)
(FE)
Framing
error
(CTS)
Clear
to send
Bit 4
(∆DCD)
Delta
data carrier
detect
Bit 3
BIT 2
Data
Bit 2
Data
Bit 2
Bit 2
Bit 10
(ERLSI)
Enable
receiver
line
status
interrupt
Tranmitter
FIFO
reset
Interrupt ID
Bit (1)
(STB)
Number of
stop bits
OUT1
(an unused
internal
signal)
(PE)
Parity
error
(TERI)
Trailing
edge ring
indicator
Bit 2
BIT 1
Data
Bit 1
Data
Bit 1
Bit 1
Bit 9
(ETBEI)
Enable
transmitter
holding
register
empty
interrupt
Receiver
FIFO
reset
Interrupt ID
Bit (0)
(WLSB1)
Word length
select bit 1
(RTS)
Request
to send
BIT 0
Data
Bit 0
(LSB)
Data
Bit 0
Bit 0
Bit 8
(ERBFI)
Enable
received
data
available
interrupt
FIFO
Enable
0 If
interrupt
pending
(WLSB0)
Word length
select bit 0
(DTR)
Data
terminal
ready
(OE)
Overrun
error
(DR)
Data
ready
(∆DSR)
Delta
data set
ready
Bit 1
(∆CTS)
Delta
clear
to send
Bit 0
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