TL16C552 Datasheet, PDF (5/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
Terminal Functions (continued)
TERMINAL
NAME
NO.
STB
55
TRI
2
TXRDY0,
TXRDY1
22, 42
VDD
23, 40, 64
I/O
DESCRIPTION
I/O Printer strobe. STB is an open-drain line that provides communication between the TL16C552 and the
printer. When it is active (low), it provides the printer with a signal to latch the data currently on the
parallel port. This terminal has an internal pullup resistor to VDD of approximately 10 kΩ.
I 3-state control. TRI controls the 3-state control of all I/O and output terminals. When TRI is asserted,
all I/O and outputs become high impedance, allowing board level testers to drive the outputs without
overdriving the internal buffers. This terminal is level sensitive, is a CMOS input, and is pulled down
with an internal resistor that is approximately 5 kΩ.
O Transmitter ready. TXRDY0 and TXRDY1 are transmitter ready signals. Two types of DMA signaling
are available. Either can be selected using FCR3 when operating in the FIFO mode. Only DMA mode
0 is allowed when operating in the TL16C450 mode. Single-transfer DMA (a transfer is made between
CPU bus cycles) is supported by mode 0. Multiple transfers that are made continuously until the
transmitter FIFO has been filled are supported by mode 1.
Mode 0. When in the FIFO mode (FCR0=1, FCR3=0) or in the TL16C450 mode (FCR0=0) and there
are no characters in the transmitter holding register or transmitter FIFO, TXRDY are active (low). Once
TXRDY is activated (low), it goes inactive after the first character is loaded into the holding register of
transmitter FIFO.
Mode 1. TXRDYx goes active (low) if in the FIFO mode (FCR0=1) when FCR3=1 and there are no
characters in the transmitter FIFO. When the transmitter FIFO is completely full, TXRDYx goes inactive
(high).
Power supply. VDD is the power supply requirement is 5 V ± 5%.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†
Supply voltage range, V_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V_DD + 0.3 V
Input voltage range, V_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range, V_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V_DD + 0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10°C to 70°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to ground (VSS).
recommended operating conditions
Supply voltage, VDD
Clock high-level input voltage, VIH(CLK)
Clock low-level input voltage, VIL(CLK)
High-level input voltage, VIH
Low-level input voltage, VIL
Clock frequency, fclock
Operating free-air temperature range, TA
MIN
4.75
2
– 0.5
2
– 0.5
0
NOM
5
MAX
5.25
VDD
0.8
VDD
0.8
8
70
UNIT
V
V
V
V
V
MHz
°C
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