TL16C552 Datasheet, PDF (12/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RCLK
CLK
8 CLK Cycles
tpd5
TL16C450 MODE
SIN
(receiver input
data)
Sample
CLK
Interrupt
(data ready or
RCVR ERR)
IOR
Start
Data Bits 5 – 8
Parity Stop
td9
50 %
Figure 9. Receiver Timing Waveforms
tpd6
Active
50 %
50 %
SIN
Sample
CLK
Trigger
Interrupt
(FCR6, 7 = 0, 0)
IOR
(RD RBR)
Line Status
Interrupt (LSI)
IOR
(RD LSR)
Start _{Data Bits 5 – 8}
Parity Stop
50 %
td9
tpd6
50 %
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50 % ^Active
50 %
tpd6
Active
50 %
50 %
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
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