TL16C552 Datasheet, PDF (6/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage
PARAMETER
TEST CONDITIONS
VOH High-level output voltage
VOL Low-level output voltage
II
Input current
II(CLK) Clock input current
IOH = – 0.4 mA for DB0 – DB7,
IOH = – 2 mA for PD0 – PD7,
IOH = – 0.4 mA for INIT, AFD, STB, and SLIN (see Note 2),
IOH = – 0.4 mA for all other outputs
IOL = 4 mA for DB0 – DB7,
IOL = 12 mA for PD0 – PD7,
IOL = 10 mA for INIT, AFD, STB, and SLIN (see Note 2),
IOL = 2 mA for all other outputs
VDD = 5.25 V,
All other terminals are floating
VI = 0 to 5.25 V
IOZ
High-impedance output current
VDD = 5.25 V,
VO = 0 with chip deselected, or
VO = 5.25 V with chip and write mode selected
IDD
Supply current
VDD = 5.25 V,
No loads on outputs,
SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1,
RI0 and RI1 at 2 V,
Other inputs at 0.8 V,
Baud rate generator fclock = 8 MHz, Baud rate = 56 kbit/s
NOTE 2: These four terminals contain an internal pullup resistor to VDD of approximately 10 kΩ.
MIN MAX UNIT
2.4
V
0.4 V
± 10 µA
± 10 µA
± 20 µA
50 mA
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
tw1
Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1)
tw2
Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1)
tw3
Pulse duration, master (RESET) low (see Figure 16)
MIN
55
55
1000
MAX
UNIT
ns
ns
ns
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN MAX
tw4
tsu1
tsu2
th1
th2
td1
td2
NOTES:
Pulse duration, IOR low
80
Setup time, chip select valid before IOR low (see Note 3)
15
Setup time, A2 – A0 valid before IOR low (see Note 3)
15
Hold time, A2 – A0 valid after IOR high (see Note 3)
20
Hold time, chip select valid after IOR high (see Note 3)
20
Delay time, tsu2 + tw4 + td2 (see Note 4)
175
Delay time, IOR high to IOR or IOW low
80
3. The internal address strobe is always active.
4. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).
UNIT
ns
ns
ns
ns
ns
ns
ns
6
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