TL16C552 Datasheet, PDF (18/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR)
This write-only register is at the same location as the IIR. It enables and clears the FIFOs, sets the trigger level
of the receiver FIFO, and selects the type of DMA signaling. The contents of FCR are described in Table 3 and
the following bulleted list.
D Bit 0: FCR0 enables both the transmitter and receiver FIFOs. All bytes in both FIFOs can be reset by
clearing FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
TL16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCR0 =1.
D Bit 1: FCR1=1 clears all bytes in the receiver FIFO and resets the counter. This does not clear the shift
register.
D Bit 2: FCR2=1 clears all bytes in the transmitter FIFO and resets the counter. This does not clear the shift
register.
D Bit 3: FCR3=1 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCR0 =1.
D Bits 4 and 5: These two bits are reserved for future use.
D Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt as shown in Table 4.
Table 4. Receiver FIFO Trigger Level
BIT
7
6
0
0
0
1
1
0
1
1
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
04
08
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled:
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is cleared.
2. IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt IIR = 04.
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. IIR = 04 (receive data available indication) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.
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