TL16C552 Datasheet, PDF (27/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 18. The MCR can be written
to and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high
input asserts a low (true) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
MODEM CONTROL REGISTER
MCR MCR MCR MCR MCR MCR MCR MCR
76 5 4 3 2 1 0
Data Terminal
Ready
0 = DTR Output High (inactive)
1 = DTR Output Low (active)
Request
to Send
0 = RTS Output High (inactive)
1 = RTS Output Low (active)
Out 1
0 = OUT1 Output High
1 = OUT1 Output Low
Out 2
0 = OUT2 Output High
1 = OUT2 Output Low
Loop
0 = Loop Disabled
1 = Loop Enabled
Bits are Cleared
Figure 18. Modem Control Register Contents
D Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel can be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
D Bit 1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel can be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
D Bit 2: When MCR2 is set, OUT1 is forced low.
D Bit 3: When MCR3 is set, the OUT2 output is forced low.
D Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output (SOUT) is set to the marking (high) state, and the SIN is disconnected. The output of the TSR
is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD, and
RI) are disconnected. The modem control outputs (DTR, RTS, OIUT1, and OUT2) are internally connected
to the four modem control inputs. The modem control output terminals are forced to their inactive state (high)
on the TL16C552. In the diagnostic mode, data transmitted is immediately received. This allows the
processor to verify the transmit and receive data paths of the selected serial channel. Interrupt control is
fully operational. However, interrupts are generated by controlling the lower four MCR bits internally.
Interrupts are not generated by activity on the external terminals represented by those four bits.
D Bits 5 – 7: These three bits(MCR5 – MCR7) are permanently cleared.
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