TL16C552 Datasheet, PDF (26/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
1. It initializes the transmitter and receiver clock counters.
2. It clears the LSR, except for TEMT and THRE, which are set. The MCR is also cleared. All of the discrete
lines, memory elements, and miscellaneous logic associated with these register bits are also cleared or
turned off. The LCR, divisor latches, RBR, and transmitter buffer register are not effected.
Following the removal of the reset condition (RESET high), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the affect of a reset on the ACE is given in Table 10.
Table 10. RESET Affects On Registers and Signals
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
Line control register
Modem control register
FIFO control register
Line status register
Modem status register
SOUT
Interrupt (receiver errs)
Interrupt (receiver data ready)
Interrupt (THRE)
Interrupt (modem status changes)
OUT2
RTS
DTR
OUT1
RESET CONTROL
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Read LSR/Reset
Read RBR/Reset
Read IIR/Write THR/Reset
Read MSR/Reset
Reset
Reset
Reset
Reset
RESET
All bits cleared (0 – 3 forced and 4 – 7
permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 cleared
Bits 4 – 5 are permanently cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared, except bits 5 and 6 are set
Bits 0 – 3 cleared, bits 4 – 7 input signal
High
Cleared
Cleared
Cleared
Cleared
High
High
High
High
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