TL16C552 Datasheet, PDF (30/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
programmable baud generator
The ACE serial channel contains a programmable baud rate generator that divides the clock (dc to 8 MHz) by
any divisor from 1 to (2¹⁶ – 1). The output frequency of the baud rate generator is 16× the data rate (divisor #
= clock ÷ (baud rate × 16)) referred to in this document as RCLK. Two 8-bit divisor latch registers store the divisor
in a 16-bit binary format. These divisor latch registers must be loaded during initialization. Upon loading either
of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The
baud rate generator can use any of three different popular frequencies to provide standard baud rates. These
frequencies are 1.8432 MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50- to
512-kbits/s are available. Tables 14, 15, and 16 illustrate the divisors needed to obtain standard rates using
these three frequencies.
Table 14. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
–
–
0.026
0.058
–
–
–
–
–
0.690
–
–
–
–
–
–
–
2.860
Table 15. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
–
–
0.026
0.034
–
–
–
–
0.312
–
–
0.628
–
1.230
–
–
–
30
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