TL16C552 Datasheet, PDF (22/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
LINE CONTROL REGISTER
LCR LCR LCR LCR LCR LCR LCR LCR
76 5 4 3 2 1 0
Word Length
Select
Stop Bit
Select
Parity Enable
Even Parity
Select
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
0 = 1 Stop Bits
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
0 = Parity Disabled
1 = Parity Enabled
0 = Odd Parity
1 = Even Parity
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
0 = Break Disabled
1 = Break Enabled
Divisor Latch
Access Bit
0 = Access Receiver Buffer
1 = Access Divisor Latches
Figure 17. Line Control Register Contents
line printer port (LPT)
The line printer port contains the functionality of the port included in the TL16C452, but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PEMD) terminal. This
enhancement is the addition of a direction control bit, and an interrupt status bit.
register 0 line printer data register (LPD)
The LPD port is either output only or bidirectional, depending on the state of the extended mode terminal and
data direction control bits.
D Compatibility mode (PEMD is low). Reads to the LPD register return the last data that was written to the
port. Write operations immediately output data to the PD0 – PD7 terminals.
D Extended mode (PEMD is high). Read operations return either the data last written to the LPT data register
when the direction bit is cleared to write, or the data that is present on PD0 – PD7 when the direction is set
to read. Writes to the LPD register latch data into the output register, but only drive the LPT port when the
direction bit is cleared to write.
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