TL16C552 Datasheet, PDF (7/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
tw5 Pulse duration, IOW low
tsu4 Setup time, chip select valid before IOW low (see Note 3)
tsu5 Setup time, A2 – A0 valid before IOW low (see Note 3)
tsu6 Setup time, D0 – D7 valid before IOW high
th3 Hold time, A2 – A0 valid after IOW high (see Note 3)
th4 Hold time, chip select valid after IOW high (see Note 3)
th5 Hold time, D0 – D7 valid after IOW high
td3 Delay time, tsu5 + tw5 + td4
td4 Delay time, IOW high to IOW or IOR low
NOTE 3: The internal address strobe is always active.
MIN MAX UNIT
80
ns
15
ns
15
ns
15
ns
20
ns
20
ns
15
ns
175
ns
80
ns
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)
PARAMETER
TEST CONDITIONS
tpd1
Propagation delay time from IOR high to BDO high or from IOR low to
BDO low
CL = 100 pF, See Note 5
ten Enable time from IOR low to D0 – D7 valid
CL = 100 pF,
tdis Disable time from IOR high to D0 – D7 released
CL = 100 pF,
NOTE 5: VOL and VOH (and the external loading) determine the charge and discharge time.
See Note 5
See Note 5
MIN MAX UNIT
60 ns
60 ns
0
60 ns
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
td5 Delay time, interrupt THRE low to SOUT low at start
TEST CONDITIONS
MIN MAX
8
24
td6 Delay time, SOUT low at start to interrupt THRE high
See Note 6
8
8
td7 Delay time, IOW (WR THR) high to interrupt THRE high
See Note 6
16
32
td8 Delay time, SOUT low at start to TXRDY low
CL = 100 pF
8
tpd2 Propagation delay time from IOW (WR THR) low to interrupt THRE low
CL = 100 pF
140
tpd3 Propagation delay time from IOR (RD IIR) high to interrupt THRE low
CL = 100 pF
140
tpd4 Propagation delay time from IOW (WR THR) high to TXRDY high
CL = 100 pF
195
NOTE 6: When the transmitter interrupt delay is active, this delay si lengthened by one character time minus the last stop bit time.
UNIT
RCLK
cycles
RCLK
cycles
RCLK
cycles
RCLK
cycles
ns
ns
ns
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