TL16C552 Datasheet, PDF (24/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line printer port (LPT) (continued)
Table 8. LPC Register Bit Description
BIT
DESCRIPTION
0
STB
1
AFD
2
INIT
3
SLIN
4
INT2 EN
5
DIR
6
Reserved (0)
7
Reserved (0)
D Bit 0: This bit is the printer strobe (STB) control bit. When this bit is set, the STB signal is asserted on the
LPT interface. When STB is cleared, the signal is negated.
D Bit 1: This bit is the auto feed (AFD) control bit. When this bit is set, the AFD signal is asserted on the LPT
interface. When AFD is cleared, the signal is negated.
D Bit 2: This bit is the initialize printer (INIT) control bit. When this bit is set, the INIT signal is negated. When
INIT is cleared, the INIT signal is asserted on the LPT interface.
D Bit 3: This bit is the select input (SLIN) control bit. When this bit is set, the SLCT signal is asserted on the
LPT interface. when SLIN is cleared, the signal is negated.
D Bit 4: This bit is the interrupt request enable (INT2 EN) control bit. When set, this bit enables interrupts from
the LPT port whenever the ACK signal is released. When cleared, INT2 EN disables interrupts and places
INT2 signal in 3-state.
D Bit 5: This bit is the direction (DIR) control bit (only used when PEMD is high). When this bit is set, the output
buffers in the LPD port are disabled allowing data driven from external sources to be read from the LPD port.
When DIR is cleared, the LPD port is in output mode.
line status register (LSR)
The LSR is a single register that provides status indications. The LSR is shown in Table 9 and is described in
the following bulleted list.
Table 9. Line Status Register Bits
LSR BITS
1
0
LSR0 data ready (DR)
Ready
Not ready
LSR1 overrun error (OE)
Error
No error
LSR2 parity error (PE)
Error
No error
LSR3 framing error (FE)
Error
No error
LSR4 break interrupt (BI)
Break
No break
LSR5 THRE
Empty
Not empty
LSR6 transmitter empty (TEMT)
Empty
Not empty
LSR7 receiver FIFO error
Error in FIFO No error in FIFO
† _{LSR is intended only for factory test. It should be considered as read only by applications software.}
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