TL16C552 Datasheet, PDF (14/33 Pages) Texas Instruments – DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
SIN
(first byte that reaches
the trigger level)
Stop
50 %
Active
See Note A
Sample
CLK
td9
(see Note B)
RXRDY
50 %
tpd7
50 %
NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCR0=1, then td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK
Figure 13. Receiver Ready Mode 1 Waveforms
IOW
(WR MCR)
RTS, DTR
CTS, DSR, DCD
INT0, INT1,
1 INT, 2 INT
IOR
(RD MSR)
RI
50 %
tpd8
50 %
tpd8
50 %
50 %
tpd9
50 %
tpd9
50 %
tpd10
50 %
50 %
50 %
tpd11
50 %
50 %
Figure 14. Modem Control Timing Waveforms
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