GC4016 Datasheet, PDF (8/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
CE
WR
RD
A[0-4]
C[0-7]
CE
WR
RD
A[0-4]
C[0-7]
CE
WR
A[0-4]
C[0-7]
CE
WR
A[0-4]
C[0-7]
t_REC
t_CSU
t_CSU
t_REC
t_CSU
t_CSU
t_CDLY
READ CYCLE- NORMAL MODE
t_CSPW
WRITE CYCLE- NORMAL MODE
t_REC
t_CZ
t_REC
t_CHD
t_REC
t_CSU
t_REC
t_CSU
t_CDLY
READ CYCLE- RD HELD LOW
t_CSPW
WRITE CYCLE- RD HELD LOW
Figure 2. Normal Control I/O Timing
t_REC
t_CZ
t_REC
t_CHD
processors that do not provide stable data before the start of
the write pulse. Figure 3 shows the timing for this mode.
The setup, hold and pulse width requirements for control
read or write operations are given in Section 6.0.
The chip also operates in a four bit address mode which
is intended to be used with the 4 address bit TI320C6X DSP
chip’s expansion bus. Address pin A3 is grounded in this
mode and the LSB of the page register (address 2) is used in
its place. The four bit mode is turned on using the
4_BIT_ADDRESS control bit in address 4.
CE
WR
RD
A[0-4]
C[0-7]
t_REC
t_CSU
t_CSU
t_CSPW
EDGE WRITE MODE
t_EWCSU
Figure 3. Edge Write Control Timing
t_REC
t_CHD
© GRAYCHIP,INC.
-3-
August 27, 2001
This document contains information which may be changed at any time without notice