GC4016 Datasheet, PDF (68/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
7.9.2 Oversampling Using the Resampler
This example assumes the input sample rate is equal to 4*N*B, where N is the decimation in the CIC filter (See Section 5.6)
and B is the GSM bit rate (270.833 KHz). The outputs are one complex sample per bit (270.833 KHz) with the resampler set to
interpolate by unity (no interpolation). The output rate can be doubled or quadrupled as desired by changing the resampler ratio.
The resampler uses the configuration res_8x64_60. (See Section 7.7). This configuration introduces 0.03dB of passband ripple
and -62dB inband noise, neither being large enough to effect the BER.
The resampler ratio for one sample per bit (270.833KHz) is 0x04000000. It is 0x02000000 for two samples per bit
(541.666KHz) and it is 0x010000000 for four samples per bit (1.08333MHz).
7.9.3 Gain
The example configuration assumes a CIC decimation of N=64, which corresponds to an ADC clock rate (CK) of 69.333248
MHz. The values of SCALE and BIG_SCALE must be chosen to satisfy: (SHIFT + SCALE + 6 × BIG_SCALE) ≤ (62 – 5log₂N) .
N is 64 and SHIFT is 4, so (SCALE + 6 × BIG_SCALE) ≤ 28 , which is satisfied by setting SCALE=4 and BIG_SCALE=4. If other
values of N are chosen, then SCALE and BIG_SCALE need to be modified as necessary. The overall gain is adjusted using
FINE_GAIN and FINAL_SHIFT. The overall gain is:
GAIN
=



(
----------¹-----------)
NZEROS + 1
N⁵
2^(SHIFT
+
SCALE
+
6
×
BIG_SCALE
–
62
)
(

2^COARSE
)
(
C_---F_--I_--R_--__--S_---U_--M_---)
65536
(
P_---F_--I_-R_---__--S_--U_---M_--
65536
)
(
F_---I_-N_---E_--__--G_---A_---I_-N_--)
1024
(
----------R----E----S---_---S---U-----M-------------
32768 × NDELAY
)
(
2
FINAL_SHIFT
)
where NZEROS=0, N=64, SHIFT=4, SCALE=4, BIG_SCALE=4, COARSE=0, CFIR_SUM=83001, PFIR_SUM=96277,
RES_SUM=134782 and NDELAY=64. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0.
This can be achieved by setting FINE_GAIN to 1070 and FINAL_SHIFT equal to 4.
7.9.4 GSM Configuration
The control register settings for this example are shown in table 30. It is assumed that output pin SO is tied to input pin SIA.
Table 30: Example GSM Configuration
Address
Address
CH A Pages 0,1
Pages 2-5
Page 6
Page 7
CH B Pages 8.9
Pages 10-13
Page 14
Page 15
CH C Pages 16,17
Pages 18-21
Page 22
Page 23
CH D Pages 24,25
Pages26-29
Page 30
Page 31
RES Page 32-63
Page 64
Page 65
OUT Page 98
Global Registers
0
1
2
3
4
5
6
7
F8 00 00 -
27 DC 00 00
Paged Registers
16 17 18 19 20 21 22 23
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_gsm.taps
00 00 FREQ
unused
0C 77 00 20 22 3F 70 64
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients pfir_gsm.taps
00 00 FREQ
unused
0C 77 00 20 22 3F 70 64
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_gsm.taps
00 00 FREQ
unused
0C 77 00 20 22 3F 70 64
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_gsm.taps
00 00 FREQ
unused
0C 77 00 20 22 3F 70 64
Load resampler coefficients: res_8x64_60.taps
23 07 00 34 E4 00 00 00
00 00 00 04 00 00 00 04
7F 40 28 01 E9 B0 E4 10
After configuration set address 0 to 08, then set address 5 to 5C
24
25
26
27
28
29
30
31
00
00
00
00
1D -
2E 04
00
00
00
00
1D -
2E 04
00
00
00
00
1D -
2E 04
00
00
00
00
1D -
2E 04
unused
00
00
00
04
00
00
00
04
32
54
76
02
unused
© GRAYCHIP,INC.
- 63 -
August 27, 2001
This document contains information which may be changed at any time without notice