GC4016 Datasheet, PDF (16/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
Double rate real output can be generated by combining
SPLITIQ and complex to real conversion. The complex to
real signal processing is the same as described in Section
3.3.7. Here however, one channel contains the real portion of
the signal and another contains the complex portion. To
convert this complex data to real, the real channel must be
delayed (set QDLY_PFIR=1), multiplied by a pattern 1,-1, 1,
-1 (set NEG_CTL=5), and QONLY should be set. The
imaginary channel should be multiplied by the sequence
-1,1,-1,1 (set NEG_CTL=10) and QONLY should be set. The
output is then available as the Q data in the selected
resampler and output channel (see CHAN_MAP_A,B,C and
D in the resampler’s control page, also see REAL_ONLY).
3.4.2 Wideband Downconvert Mode
Even wider output bandwidth is possible by combining
all four channels. This is done by noticing that PFIR
decimates the signal by two. If one pair of channels in the
SPLITIQ mode are used to generate even time sample
outputs and the other pair are used to generate odd time
sample outputs, then the PFIR filter effectively does not
decimate the signal. This allows a wider bandwidth filter to be
used in the CFIR and PFIR. Adjacent channel rejection,
however, will be reduced due to the increase in the output
bandwidth relative to the CIC’s stopbands. Also the increase
in output bandwidth makes it harder for the CFIR and PFIR
to achieve deep stop bands. Fortunately, signals that require
wideband processing are also typically signals that do not
require as much stop band rejection as narrowband signals
such as GSM.
The wide output mode uses the chip in the SPLITIQ
mode described in Section 3.5.1. In addition the QDLY_PFIR
bits are set in channels A and B. The delay of one input
sample into the PFIR will offset the decimate by two
operation so that the channel A and B outputs are the real
and imaginary parts of the even time samples and the C and
D outputs are the real and imaginary parts of the odd time
samples. This mode is used in the example UMTS
configuration described in Section 7.12.
Performing real to complex conversion in this mode
involves setting the controls as above, but also setting
QDLY_CFIR on channels A and C; setting NEG_CTL to 15
for channels B and C; setting QONLY=1 (and IONLY=0) for
all channels.
3.4.3 Complex Input, Narrowband output
Complex input data can be processed using two
channels. The real portion of the input (I_IN) is processed in
one channel while the imaginary portion (Q_IN) is processed
in the next channel. Channels A and B are described here,
channels C and D can be combined as well. The desired
mixer output is I_OUT=(I_IN*cos-Q_IN*sin) and
Q_OUT=(I_IN*sin+Q_IN*cos). Channel A is used in the normal
mode and will output (I_IN*cos) and (I_IN*sin). A 90 degree
offset (PHASE=0x4000) in channel B will cause channel B to
output (-Q_IN*sin) and (Q_IN*cos). The desired result is
achieved by adding the channel A outputs to the channel B
outputs in the resampler. The resampler is told to add the
channels together by setting the ADD_A_TO_B bit for
channel A in the resampler’s control page.
The complex to real mode described in Section 3.3.7
can be used in conjunction with the complex input mode. If
both channels are configured as described in Section 3.3.7,
then the combined complex input downconverter will be in
the complex to real mode.
3.4.4 Complex Input, Double Bandwidth
(SplitI/Q) Mode
The complex input and SPLITIQ modes can be
combined. Channels A and D will process the I_IN inputs.
Channels B and C will process the Q_IN input data. Channel A
will output (I_IN*cos). Channel B will output (-Q_IN*sin) if its
phase is set to 90 degrees (PHASE=0x4000). Channel C will
output (Q_IN*cos). Channel D will output (I_IN*sin) if its phase is
set to -90 degrees (PHASE=0xC000). The I_OUT output is
formed by adding channel A to channel B, and the Q_OUT
output is formed by adding channel C to channel D. The
IONLY bits must be set for channels A and B, and the
QONLY bits must be set for channels C and D.
The complex to real mode can be added to this mode by
delaying the I word by half (set QDLY_PFIR in channels A
and B) and mixing by Fs/4 (set NEG_CTL to 5 in channels A
& B and set NEG_CTL to 10 in channels C & D). QONLY
instead of IONLY needs to be set in channels A and B.
3.4.5 Multichannel Summary
Table 2 summarizes the settings for the eight
multichannel modes. A phase setting of 90 indicates a +90
degree phase offset, or a value of 0x4000. A phase setting of
-90 indicates a -90 degree phase offset, or a value of
0xC000.
© GRAYCHIP,INC.
- 11 -
August 27, 2001
This document contains information which may be changed at any time without notice