GC4016 Datasheet, PDF(29/83 Page) Texas Instruments

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GC4016 Datasheet, PDF (29/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

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GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

3.10 POWER DOWN MODES

The 3 bit sync mode control for each sync circuit is

defined in Table 7:

The chip has a power down and clock loss detect circuit.

This circuit detects if the clock is absent long enough to

Table 7: Sync Modes

cause dynamic storage nodes to lose state. If clock loss is

detected, an internal reset state is entered to force the

dynamic nodes to become static. The control registers are

not reset and will retain their values, but any data values

within the chip will be lost. When the clock returns to normal

the chip will automatically return to normal. In the reset state

MODE

0,1

SYNC SOURCE

off (never asserted)

SIA

SIB

ONE_SHOT

the chip consumes only a small amount of standby power.

TC (terminal count of internal counter)

The user can select whether this circuit is in the automatic

6,7

on (always active)

clock-loss detect mode, is always on (power down mode), or

is disabled (the clock reset never kicks in) using the

NOTE: the internal syncs are active high. The SIA and

CK_LOSS_DETECT and GLOBAL_RESET control bits in

SIB inputs have been inverted to be the active high syncs SIA

address 0. The whole chip, or individual down converter

and SIB in Table 7.

channels can be powered down.

The ONE_SHOT can either be a level or a pulse as

NOTE: Resampler channel 0 provides the âblock

selected by the OS_MODE control bit. The level mode is

completeâ signal to the output FIFO when

used to initialize the chip, the pulse mode is used to

OUTPUT_ORDER=1 or 2. This means that the channel

synchronously switch frequency, phase or gain values.

feeding resampler channel 0, typically channel A (see

CHAN_MAP in the resampler control page), can not be

powered down when OUTPUT_ORDER=1 or 2.

Typically the decimation counters (DEC_SYNC), the

flush circuits (FLUSH_SYNC) and the output block sync

(OUT_BLK_SYNC) will be set to SIA, while the NCO phase

3.11 SYNCHRONIZATION

accumulator syncs (NCO_SYNC) will be set to SIB. The SIA

input can then be used to initialize and flush the channels and

Each GC4016 chip can be synchronized through the use

of one of two sync input signals, an internal one shot sync

generator, or a sync counter. The sync to each circuit can

also be set to be always on or always off. Each circuit within

the SIB sync input can be used, if desired, to synchronize the

phases of the NCOs.

The recommended sync mode settings are summarized

in Table 8.

the chip, such as the sine/cosine generators or the

decimation control counter can be synchronized to one of

these sources. These syncs can also be output from the chip

so that multiple chips can be synchronized to the syncs

coming from a designated âmasterâ GC4016 chip.

The SIA and SIB sync inputs are either connected to a

user defined sync generator, for example, an FPGA, or are

tied to a GC4016 chipâs sync output pin (SO). If there are

multiple GC4016 chips in the system, then the SO pin of one

chip can be used to drive the SIA input of all chips, and the

SO pin of another chip can drive the SIB inputs of all chips.

Table 8: Recommended Sync Settings

Global Syncs (Addresses 4 and 5)

Sync

DIAG_SYNC

OUTPUT_SYNC

COUNTER_SYNC

Value

7 (always)

4 (OS)

Description

Only used during diagnostics

The SO output is used during initialization

Sync counter with one shot pulse

Output Circuit Sync (Page 98)

OUT_BLK_SYNC 2 (SIA)

Sync the output block during initialization

Resampler syncs (Page 64)

RES_SYNC

2 (SIA)

RATIO_SYNC

7(always)

Sync the Resampler during initialization

Set to always except when synchronously

changing ratios

Channel Syncs (Pages 7, 15, 23 and 31)

Sync

PHASE_SYNC

FREQ_SYNC

NCO_SYNC

DITHER_SYNC

ZPAD_SYNC

DEC_SYNC

FLUSH_SYNC

GAIN_SYNC

PEAK_SYNC

Value

7 (always)

2 (SIA)

0 (never)

or 2 (SIA)

2 (SIA)

7 (always)

5 (TC)

Description

Use phase settings as they are loaded

Use frequency settings as they are loaded

Sync the phase accumulator during

initialization. Set to SIB for frequency

hopping.

Can free run except during diagnostics, or

reset during initialization

Sync the zero pad circuit during initialization

Sync the channel decimation during

initialization

Flush the channels during initialization

Use fine gain settings as they are loaded

Periodically capture peak count data

- 24 -

August 27, 2001

This document contains information which may be changed at any time without notice

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