GC4016 Datasheet, PDF (73/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
7.11.4 IS95 NB-CDMA Configuration
The control register settings for this example are shown in table 34. It is assumed that output pin SO is tied to input pin SIA.
Table 34: Example IS95 NB-CDMA Configuration
Address
Address
CH A Pages 0,1
Pages 2-5
Page 6
Page 7
CH B Pages 8.9
Pages 10-13
Page 14
Page 15
CH C Pages 16,17
Pages 18-21
Page 22
Page 23
CH D Pages 24,25
Pages26-29
Page 30
Page 31
RES Page 32-63
Page 64
Page 65
OUT Page 98
Global Registers
0
1
2
3
4
5
6
7
F8
00
00
-
27
DC 00
00
Paged Registers
16
17
18
19
20
21
22
23
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_is95_1.5x.taps
00
00
FREQ
unused
0C 77
22
20
22
07
70
79
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients pfir_is95_1.5x.taps
00
00
FREQ
unused
0C 77
22
20
22
07
70
79
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_is95_1.5x.taps
00
00
FREQ
unused
0C 77
22
20
22
07
70
79
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_is95_1.5x.taps
00
00
FREQ
unused
0C 77
22
20
22
07
70
79
Load resampler coefficients: res_6x64_60.taps
23
05
00
14
E4
70
00
E4
00
00
80
01
00
00
80
01
FF
40
6C 87
EF 00
E4
10
After configuration set address 0 to 08, then set address 5 to 5C
24
25
26
27
28
29
30
31
00
00
00
00
1D
-
81
04
00
00
00
00
1D
-
81
04
00
00
00
00
1D
-
81
04
00
00
00
00
1D
-
81
04
unused
00
00
80
01
00
00
80
01
32
54
76
02
unused
7.12 UMTS WB-CDMA APPLICATION
This section describes how to configure the chip to downconvert UMTS WB-CDMA signals and output samples at two times
or four times the UMTS symbol rate. The desired UMTS Specifications are:
Table 35: Desired UMTS Specifications
Specification
Clock (CK)
Input Sample Rate
Input Format
Spur free dynamic
range
Output Sample Rate
Passband Width
Passband Ripple
Stopband Rejection
Output Format
Value
61.44MHz =16*3.84MHz
Same as clock rate
A port, 14 Bit, 2’s Complement
> -80dB
Comment
Can be any value greater than this, does not need to be a multiple of 3.84MHz.
May be an integer division of the clock rate (30.72MHz, 20.48MHz, etc.)
Can be modified as desired
The GC4016 NCO provides more than 115 dB of spur free dynamic range
15.36MSPS, complex data (4X)
4.6848MHz
0.1 dB
60 dB at 5MHz, 80dB at > 5MHz offset
Parallel output, 16 bit I and Q data
Can be 2X or 4X multiple of the symbol rate by changing the resampler ratio. Can do two
channels at 2X if the clock rate is greater than 92.16MHz.
RRC filter with alpha=0.22 give a bandwidth of 1.22*3.84MHz
Filter gives 0.05dB passband ripple
Rejection > 80dB at 2.6MHz offset
Can be modified as desired, allows simple AGC in an FPGA to 4 or 6 bits.
© GRAYCHIP,INC.
- 68 -
August 27, 2001
This document contains information which may be changed at any time without notice