GC4016 Datasheet, PDF(17/83 Page) Texas Instruments

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GC4016 Datasheet, PDF (17/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

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GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

Table 2: Multichannel mode settings

Input

Output

Rate

Output

Format

Channel

Real

Complex

Two 2X output channels

Single 4x output channel

Complex

Real

Complex

Real

Complex

A B C D ABCDABCDABCDAB CD

Real

Complex

Real

AB CDAB

SPLITIQ 1

PHASE

QDLY_CFIR 0

IDLY_PFIR 0

QDLY_PFIR 0

NEG_CTL 0

IONLY

QONLY

ADD_TO 0

CHAN_MAP 0

90 0

10 5

90 0

10 0

90 0

1110

90 0 90 0

0100

0000

1000

15 15 0 0

0000

1110

0001

0000

90 0

-90 0

1 11

90 0 -90

0 00

1 00

5 10 10

0 00

1 11

0 10

0 00

3.5 RESAMPLER

The resampler will independently filter and change the

data rate of each channel. The most common application of

the resampler is to increase the sample rate of the data so

that it will match a desired symbol or bit rate. Demodulators

for digital modulation schemes, such as GMSK, QPSK, QAM

or CDMA, for example, require sample rates which are 1X,

2X, 4X or 8X times the bit or symbol rate of the modulation.

In these cases, the maximum down converter filter

performance is achieved when the PFIR output rate is

around 1.5 to 2 times the signalâs bandwidth1. The resampler

is then used to increase the sample rate up to the required

2X, 4X or 8X rate.

Section 7.7 shows example resampler configurations

and their performance.

The resampler can also be used as an additional filter to

optimize the passband or stopband response of the channel.

1. The PFIRâs 63 tap filterâs stopband, transition band and passband ripple

performance improves as its output rate decreases relative to the signalâs

bandwidth. The resamplerâs performance, however, begins to decrease when

the PFIR output rate is below 1.5 times the signalâs bandwidth.

Interpolation Filter

3.5.1 Functional Description

The resampler consists of an input buffer, an

interpolation filter, and a final shift block. A functional block

diagram of the resampler is shown in Figure 12.

The resamplerâs sampling rate change is the ratio

NDELAY/NDEC where NDELAY and NDEC are the

interpolation and decimation factors shown in Figure 12. The

decimation amount NDEC is a mixed integer/fractional

number. When NDEC is an integer, then the exact sampling

instance is computed and there is no phase jitter. If NDEC is

fractional, then the desired sampling instance will not be one

of the possible NDELAY interpolated values. Instead the

nearest interpolated sample is used. This introduces a timing

error (jitter) of no more than 1/(2*NDELAY) times the input

sample period.

The input buffer accepts 24 bit data from the four input

channels, and adds them as necessary to form 1,2, or 4

resampler channels (see the ADD_TO control bits in address

21 of the resampler control page). The input buffer serves

both as a FIFO between the channels and the resampler,

and as a data delay line for the interpolation filter. The 64

complex word input buffer can be configured as four

segments of 16 complex words each to support 4 resampler

Fractional

Decimation

INPUT

BUFFER

NDELAY

QTAP Filter Coefs

NDEC

FINAL

SHIFT

AND

ROUND

OUT

Resampling Filter

Figure 12. Resampler Channel Block Diagram

- 12 -

August 27, 2001

This document contains information which may be changed at any time without notice

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