GC4016 Datasheet, PDF (21/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
is set. The user can clear this bit by writing a 0 to the register.
The control bit indicates that at least one sample overflowed
since the last time the bit was cleared. Since the datapath
going into the resampler is 24 bits, it is recommended that the
gain be set such that this overflow never occurs. The second
overflow point is at the resampler output. The user can check
for these overflows by examining the chip’s output data for
maximum (saturated) values.
3.8 OUTPUT MODES
Data from the resampler can be output in one of several
modes:
(1) The microprocessor mode where the outputs
are read from the 8 bit control port,
(2) The wide word microprocessor mode where
the outputs are read as 32 bit integers from a
wide word control port,
(3) The synchronous serial mode where the
outputs are output through one or more of the
four serial ports,
(4) The asynchronous serial mode where the
channels are output on the same serial stream,
but have their own serial frame sync,
(5) The nibble mode where the outputs are output
in a 4-bit at a time nibble serial format,
(6) The link mode which is compatible with the four
bit SHARC link port, or
(7) The parallel mode which outputs the data as 24
bit words.
Only one mode is supported at a time. The output
modes are controlled by writing to addresses 16 through 26
within page 98 (the output control page).
A FIFO memory holds blocks of resampler output data,
where each block contains one, two or four complex samples
as specified by the BLOCK_SIZE control in address 20. The
FIFO is used to buffer the data rate between the resampler
and the output. The number of blocks held in the FIFO
depends upon the output mode being used.
The data from the resampler can be rounded to 12,16,
20 or 24 bits. The BITS_PER_WORD control in address 20
will set the serial mode word size to be between 12 and 32
bits, or to set nibble and link mode words to be either 16 or
32 bits. If the output word size is larger than the resampler’s
output size, then the unused LSBs are cleared.
Tag bits (four bits per tag) may be programmed to
replace the four LSBs of the specified output word size. The
tags are used to identify the source of the data. The user can
program eight different tag values in addresses 23, 24, 25
and 26, two for each of the four complex output words. Tags
are enabled using the TAG_EN control bit in address 17. A
special 2 bit tag mode control (TAG_22 in address 19 of the
resampler control page) can be used to output 24 bit words
containing 22 bits of data and 2 bits of tag.
The chip supports different decimation ratios and/or
different resampling ratios for each channel. If different ratios
are used, or if the channels have not been synchronized
using the DEC_SYNC controls (See Section 3.11), then the
channels are asynchronous and tag bits are required in order
to sort out the channel data. If the same ratios are used, and
the channels have been synchronized, then the output is
synchronous and the tag bits are not required.
If the complex to real conversion modes of the PFIR
described in Section 3.3.7 are used, then the REAL_ONLY
control bit in address 18 can be used to output real rather
than complex data. The REAL_ONLY control can only be
used if all of the channels are in the complex to real mode, a
mix of complex and real data is not allowed. If the complex
output format is used to output real data (REAL_ONLY=0),
then the real outputs are output as the Q-half of the complex
output words. The I-half should be ignored.
The suggested control register settings for each of the
output modes are shown in Table 3. These settings assume
all four channels are active and the outputs are synchronous.
The output circuitry is reset upon power up. It is enabled
by clearing the OUT_BLK_RESET and PAD_RESET bits in
address 0. See Section 3.12 for the proper initialization
procedures.
An output block sync is provided (OUT_BLK_SYNC in
address 17) which can be used to synchronize the serial
clocks of multiple chips. See Section 3.12 for the proper
synchronization sequences.
3.8.1 Microprocessor Mode
In the microprocessor mode (OUTPUT_MODE=0 in
address 18) the outputs are read in bytes from the control
port. The outputs are accessed by reading addresses 16
through 31 in pages 96 and 97.
The output FIFO buffers two blocks of complex samples
in this mode. One block is accessed through the
microprocessor port as another block is being filled with new
data. When the new block is filled, the FIFO swaps the blocks
so that the user can access the new data. The block size is
usually set to buffer four complex samples per block
(BLOCK_SIZE=3). If only one or two channels are being
output, then the block size may be reduced, but it is
suggested to keep it at four samples per block in order to
© GRAYCHIP,INC.
- 16 -
August 27, 2001
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