GC4016 Datasheet, PDF (38/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
ADDRESS 4:
General Sync Register, Suggested default = 0x27, Cleared by power up
BIT
0-2
(LSB)
3-5
6
TYPE
R/W
R/W
R/W
7 (MSB) R/W
ADDRESS 5:
NAME
DIAG_SYNC
OUTPUT_SYNC
4_BIT_ADDRESS
DIFF_IN
DESCRIPTION
The Checksum generator is strobed by this sync. See Table 7 for the possible
sync selections.
The selected sync is inverted and output on the SO pin. See Table 7.
This mode allows four address bits (such as the expansion bus of the
TI320C6202) instead of 5 to be used. In this mode each page contains 8 words
(rather than 16). The LSB of the page register is used as address bit A3. Pin A3
should be grounded in this mode.
Enables differential receivers. Both this bit and the corresponding bits in each
channel must be set to properly receive differential signals. This bit should be
cleared for other inputs and for minimum power consumption.
Contact Graychip for the use of the differential input mode.
Count Sync Register, Suggested default = 0x50
BIT
0-1 LSB
TYPE
R/W
2-4
R/W
5
R/W
6
R/W
7 (MSB) R/W
ADDRESS 6:
NAME
DIAG_SOURCE
COUNTER_SYNC
COUNT_TEST
OS_MODE
ONE_SHOT
DESCRIPTION
This two bit field selects the diagnostic input source used when the INPUT_SEL
field in each channel’s control register is set to 6 or 7 (See channel control
address 27). DIAG_SOURCE = 0 selects the 16 LSB’s of the counter (see
addresses 6&7) as a diagnostic ramp. DIAG_SOURCE=1 is a zero input,
DIAG_SOURCE=2 is unused, DIAG_SOURCE= 3 gives a 0x4000 constant
input.
Synchronizes the sync counter. This counter is used to generate the periodic TC
sync. See Table 7.
Used during factory tests. Should be set to 0 for normal operation.
The ONE_SHOT signal is a level, not a pulse when this bit is set.
The one shot sync signal (OS) is generated when this bit is set. If OS_MODE is
low, then a one shot pulse (one clock cycle wide) is generated. If OS_MODE is
high, then the ONE_SHOT sync is active while this bit is high. This bit must be
cleared before another one shot pulse can be generated.
Counter Byte 0, Suggested default = DEC (CIC decimation value)
BIT
TYPE
NAME
0-7
R/W
CNT[0:7]
DESCRIPTION
The LSBs of the counter cycle period
ADDRESS 7:
Counter Byte 1, Suggested default = DEC
BIT
TYPE
NAME
0-7
R/W
CNT[8:15]
DESCRIPTION
The 8 MSBs of the counter cycle period
The chip’s internal sync counter counts in cycles of 256(CNT+1) clocks. A terminal count signal (TC) is output at the end of
each cycle. The counter can be synchronized to an external sync as specified in the Count Sync Register (address 5). If CNT is
set so that 256(CNT+1) is a multiple of sixteen times the CIC decimation ratio (i.e., a multiple of 16N), then the terminal count of
this counter can be output on the SO pin and used to periodically synchronize multiple GC4016 chips.
© GRAYCHIP,INC.
- 33 -
August 27, 2001
This document contains information which may be changed at any time without notice