GC4016 Datasheet, PDF (15/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
to determine when a new fine gain setting takes effect. It is
normally set to take effect immediately, but can be used to
synchronize the gain changes between multiple channels in
a beam forming system.
PFIR also contains a one PFIR sample input delay that
is independently programmable for the I and Q paths and for
the four channels (QDLY_PFIR and IDLY_PFIR in address
26). The delay is used when combining channels to allow
wider output bandwidth and/or more oversampling. It is also
used for complex to real conversion in PFIR.
3.3.7 Complex to Real Mode
PFIR can be used to convert from the complex format to
a real format for users desiring real output. This mode uses
PFIR to low pass filter the signal so it resides from -F_PFIR/4 to
F_PFIR/4, where F_PFIR is the sample rate into the PFIR (in this
mode PFIR does not decimate by two so it is also the output
sample rate). The signal is then mixed up by F_PFIR/4 (so it
now resides from 0 to F_PFIR/2) and the imaginary portion is
discarded. In implementation, the samples to be discarded
are never generated. This is implemented by delaying the I
data by 1 input sample (set IDLY_PFIR in address 26 of the
channel’s control page) and mixing the PFIR output with
F_PFIR/4 (set NEG_CTL=6 in address 24 of the channel’s
control page). The QONLY flag in address 24 of the
channel’s control page also needs set (The Q-half, rather
than the I-half is used due to hardware details). When
outputting real data the sample rate out of the PFIR filter is
F_CK/(2N).
The REAL_ONLY bit in address 18 of the output control
page can be set to tell the output section to output real
samples. If this bit is not set, then the output will be in a
complex format with the real samples in the Q-part of the
complex word. The REAL_ONLY mode reduces the data
rate out of the chip. Note that the REAL_ONLY bit effects all
channels, so the chip does not support some channels
outputting complex data while other channels output real
data.
3.4 MULTICHANNEL MODES
The GC4016 chip contains four independent channels
and each channel can output complex sample rates up to
Fck/32¹. Depending on the filter coefficients and the clock
rate, the maximum single channel output bandwidth is just
under 2MHz. This output bandwidth can be doubled by
1. The Resampler (Section 3.5) can be used to increase this rate for
oversampling.
combining two channels using the SPLITIQ mode. Four
channels may be combined to provide 3 to 4 times the single
channel output bandwidth (with reduced out of band
rejection). The two or four multichannel modes may also be
used in the complex to real mode described in Section 3.4.6.
Two channels can also be combined to process complex
input data, thereby doubling the input bandwidth going into
the chip.² Four channels can be combined to both process
complex input data and to double the output bandwidth of the
chip.
Combined channels are assigned to a single resampler
or output channel using the channel map controls
(CHAN_MAP_A, B, C and D) in the resampler’s control page.
Finally, for digital modulation formats, the resampler
allows the downconverter’s output sample rate to be
between 1.5 and 2 samples per baud (symbol). The
resampler will then up-sample this to exactly 2 or 4 samples
per baud. This allows the GC4016 chip to downconvert one
4X oversampled signal at symbol rates up to 8 MBaud, or two
4X oversampled signals at 3MBaud, or four 4X oversampled
signals at 1.5MBaud (assuming a 100MHz clock rate).
3.4.1 Double Bandwidth Downconverter
Mode (SplitI/Q Mode)
Two channels work together in the SplitI/Q mode to
double the output bandwidth of the downconverter. In the
splitI/Q mode the real half of the complex output data is
processed in one channel and the imaginary half in the other.
In the splitIQ mode the CIC has a minimum decimation of 4
instead of 8, which allows channel output sample rates up to
F_CK/16. The two channels being combined in the splitI/Q
mode should be programmed identically, including the tuning
frequency, except that the imaginary channel should have a
+90 degree phase shift (PHASE=0x4000). The IONLY bit in
the real channel should be set and the QONLY bit in the
imaginary channel should be set. This mode is used in the
example UMTS configuration described in Section 7.12.
Typically the chip is configured in the SPLITIQ mode so
that channels A and B are combined as one downconverter
and C and D are combined as the other. Mixed modes may
be used, such as having A and B used as narrowband
downconverters while C and D are combined into a double
bandwidth
downconverter.
The
resampler’s
CHAN_MAP_A,B,C and D controls must be set so that the
combined channels point to the same resampler channel.
2. The GC2011A digital filter chip can be used to convert sample rates up to
200MSPS into complex sample rates up to 100 MSPS. One GC2011A chip will
convert 12 bit data, two chips will convert 24 bit data.
© GRAYCHIP,INC.
- 10 -
August 27, 2001
This document contains information which may be changed at any time without notice