GC4016 Datasheet, PDF (28/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
SCK
SFS (I Valid)
RDY (Q Valid)
P[0:23]
AI0
AQ0 BI0
BQ0 CI0
CQ0 DI0
DQ0
(a) Synchronous Channels, SFS_MODE=0, BLOCK_SIZE=3
SCK
SFS (I or Q Valid)
RDY (Frame Start)
P[0:23]
AI0
AQ0 BI0
BQ0 CI0
CQ0 DI0
DQ0
(b) Synchronous Channels, SFS_MODE=2, BLOCK_SIZE=3
AI1
AQ1 BI1
AI1
AQ1 BI1
SCK
SFS (I Valid)
RDY (Q Valid)
P[0:23]
AI0
AQ0
BI0
BQ0
(c) Asynchronous Channels, SFS_MODE=0, BLOCK_SIZE=0
CI0
CQ0
SCK
SFS (I or Q Valid)
RDY (Frame Start)
P[0:23]
AI0
AQ0
BI0
BQ0
CI0
CQ0
(d) Asynchronous Channels, SFS_MODE=2, BLOCK_SIZE=0
Figure 16. Parallel Mode Timing
If SFS_MODE is 2 or 3, then SFS is a data valid flag (I
or Q) and the RDY output is a start of frame flag which
identifies the I part of channel A. If the outputs are
synchronous, then the channel data can be identified by its
position in the frame relative to the RDY flag. If the outputs
are asynchronous, then tags must be used to identify the
channel data. The parallel output timing is illustrated in
Figure 16. Note that when SFS_MODE is 2 or 3, then the
RDY flag goes high at the end of the frame and goes low after
the first word of the next frame. This is illustrated in Figures
16 b and d.
The polarities of the SFS and RDY flags are controlled
by the INV_SFS and INV_RDY bits in address 17.
3.9 CLOCKING
The clock rate is equal to the input data rate which can
be up to 80 <TBD 90> MHz. An internal clock doubler
doubles the clock rate so that the internal circuitry is clocked
at twice the data rate. The clock doubler requires a
continuous clock (no deleted clock pulses) for proper
operation.
The DVAL input is used as an active low data valid
signal which is clocked into the chip on the rising edge of CK.
The data in the next CK cycle is ignored when DVAL is high.
The DVAL signal operates by gating the output of the clock
doubler. It does not affect the clock to the output circuitry, so
the output will continue while DVAL is high. The DVAL signal
allows users to input data in bursts, such as data which is
being read from a memory or FIFO. The DVAL signal should
never be high for more than a 1msec. Normally DVAL will be
grounded.
The clock doubler can be bypassed and an externally
generated 2X clock can be used in its place by setting the
CK_2X_EN control bit in address 0. In this mode the DVAL
pin becomes the external CK_2X input. This mode is
intended for test purposes only.
The CK_2X_TEST control bit in address 0 enables the
clock test mode where the internal doubled clock is output on
the SO pin. The DVAL pin must be low in this test mode.
© GRAYCHIP,INC.
- 23 -
August 27, 2001
This document contains information which may be changed at any time without notice