GC4016 Datasheet, PDF (70/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
ratio. The resampler uses the configuration res_15x32_80. (See Section 7.7). This configuration introduces 0.05dB of passband
ripple and -58dB inband noise, neither being large enough to effect the BER.
The resampler ratio for two samples per symbol (48.6KHz) is 0x04000000, for four samples per symbol (97.2KHz) is
0x02000000, and for eight samples per symbol (194.4KHz) is 0x01000000.
7.10.3 Gain
The example configuration assumes a CIC decimation of N=320, which corresponds to an ADC clock rate (CK) of 62.208
MHz. The values of SCALE and BIG_SCALE must be chosen to satisfy: (SHIFT + SCALE + 6 × BIG_SCALE) ≤ (62 – 5log₂N) .
N is 320 and SHIFT=4, so (SCALE + 6 × BIG_SCALE) ≤ 16.4 , which is satisfied by setting SCALE=4 and BIG_SCALE=2. If
other values of N are chosen, then SCALE and BIG_SCALE need to be modified as necessary. The overall gain is adjusted using
FINE_GAIN and FINAL_SHIFT. The overall gain is:
GAIN
=



(
----------¹-----------)
NZEROS + 1
N⁵
2^(SHIFT
+
SCALE
+
6
×
BIG_SCALE
–
62
)
(

2^COARSE
)
(
C_---F_--I_--R_--__--S_---U_--M_---)
65536
(
P_---F_--I_-R_---__--S_--U_---M_--
65536
)
(
F_---I_-N_---E_--__--G_---A_---I_-N_--)
1024
(
----------R----E----S---_---S---U-----M-------------
32768 × NDELAY
)
(
2
FINAL_SHIFT
)
where NZEROS=0, N=320, SHIFT=4, SCALE=4, BIG_SCALE=2, COARSE=0, CFIR_SUM=83001, PFIR_SUM=119387,
RES_SUM=66554 and NDELAY=32. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0.
This can be achieved by setting FINE_GAIN to 1147 and FINAL_SHIFT equal to 4.
7.10.4 DAMPS Configuration
The control register settings for this example are shown in table 32. It is assumed that output pin SO is tied to input pin SIA.
Table 32: Example DAMPS Configuration
Address
Address
CH A Pages 0,1
Pages 2-5
Page 6
Page 7
CH B Pages 8.9
Pages 10-13
Page 14
Page 15
CH C Pages 16,17
Pages 18-21
Page 22
Page 23
CH D Pages 24,25
Pages26-29
Page 30
Page 31
RES Page 32-63
Page 64
Page 65
OUT Page 98
Global Registers
0
1
2
3
4
5
6
7
F8
00
00
-
27
DC 00
00
Paged Registers
16
17
18
19
20
21
22
23
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_damps_2x.taps
00
00
FREQ
unused
0C 77
00
20
22
3F
71
54
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients pfir_damps_2x.taps
00
00
FREQ
unused
0C 77
00
20
22
3F
71
54
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_damps_2x.taps
00
00
FREQ
unused
0C 77
00
20
22
3F
71
54
Load CFIR coefficients: cfir_68.taps
Load PFIR coefficients: pfir_damps_2x.taps
00
00
FREQ
unused
0C 77
00
20
22
3F
71
54
Load resampler coefficients: res_15_32_80.taps
23
0E
00
34
E4
00
00
00
00
00
00
04
00
00
00
04
7F
40
28
01
D9 B1
E4
10
After configuration set address 0 to 08, then set address 5 to 5C
24
25
26
27
28
29
30
31
00
00
00
00
1D
-
7B
04
00
00
00
00
1D
-
7B
04
00
00
00
00
1D
-
7B
04
00
00
00
00
1D
-
7B
04
unused
00
00
00
04
00
00
00
04
32
54
76
02
unused
© GRAYCHIP,INC.
- 65 -
August 27, 2001
This document contains information which may be changed at any time without notice