GC4016 Datasheet, PDF (25/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
samples) using the WORDS_PER_FRAME control in
address 20. The WORDS_PER_FRAME control is usually
set to match the number of active output channels
multiplexed onto each serial pin using the NSERIAL control.
In real output modes each sample is one word. In complex
output modes each sample is two words. NOTE:
FRAME_LENGTH must be greater than or equal to
WORDS_PER_FRAME.
If the selected number of words have been output, and
the frame is not complete, or a new FIFO block is not ready,
then the frame strobe (SFS) will remain inactive, the data bits
will go tristate, and the serial clock (SCK) will continue. In this
case a new frame will start on the next SCK pulse after the
frame completes and a new FIFO block is ready. If new
outputs are ready before the previous frame is finished, then
the FIFO will buffer the new data until the previous frame is
complete. THE FRAME LENGTH AND SERIAL CLOCK
RATES MUST BE SET SO THAT THE FRAME RATE IS
GREATER THAN OR EQUAL TO THE AVERAGE
RESAMPLER OUTPUT RATE. This means that:
(Average # of clocks per resampler output) ≥
(Frame length)(bits per word)(clocks per bit)
where the average # of clocks per resampler output is equal
to:
(Average # of clocks per resampler output) =
(Channel deciation)(NDEC/NDELAY)
and NDEC/NDELAY is the resampling ratio (see Section
3.5.1).
The frame strobe signal (SFS) is programmable to come
once per frame, once per complex word, or once per word
using the SFS_MODE control in address 19. SFS is one SCK
clock cycle wide and always comes one SCK ahead of the
first output bit in the transfer. Its polarity is programmable
(INV_SFS in address 17). If the outputs are synchronous and
the frame strobe signal is once per frame, then a word’s
position in the frame relative to the SFS strobe can be used
to identify which channel each sample belongs to. If not, tags
may be used to identify channels. Some processors require
an SFS strobe with each word so the position within a frame
relative to the SFS strobe cannot be used to identify
channels. Tag bits must be used for these processors, but
may be turned off once synchronization has been achieved.
Note that frames can be generated back to back, specifically,
the frame strobe can occur at the same time as the last bit in
the previous frame.
The serial frame timing is illustrated below in Figure 15.
Synchronous data from multiple chips may be time
division multiplexed (TDM) onto the same serial bus. A
master GC4016 chip (MASTER=1 in address 18 and
EN_RDY=1 in address 16) provides the frame strobe signal
and serial clock and a RDY start of frame pulse. The
bidirectional RDY pin is an output pin from the master chip
and is an input pin for the slave chips (MASTER=0,
EN_RDY=0). The slave chips use the RDY input frame
strobe to identify the start of frame. The master will drive the
serial outputs for the first 1-8 words
(WORDS_PER_FRAME) of the frame, and then will tristate
its serial data out. The slave chips are programmed using the
FRAME_LENGTH control to delay the start of their outputs
by 1-63 words from the beginning of frame. Note that the
delay is programmed in words, NOT complex samples. The
delay can be programmed independently for each slave chip
so that each chip can have its own block of time in which to
output data. For example, a four chip TDM stream can be
generated, where each chip is outputting eight words (four
complex outputs), by setting WORDS_PER_FRAME=7 (8
words per chip) in all four chips, FRAME_LENGTH=31 in the
master chip (32 words per frame), FRAME_LENGTH=7 in
the second chip (start at word 8), FRAME_LENGTH=15 in
the third chip (start at word 16) and FRAME_LENGTH=23 in
the fourth chip (start at word 24).
The TDM mode requires that the serial clocks in the
master and slave chips have been synchronized using the
OUT_BLK_SYNC control. See Section 3.12 for details.
The TDM mode is intended for use with a single serial
output stream (NSERIAL=0), but will also work with one, two
or four streams. The TDM outputs are then identified within
each stream according to the NSERIAL and
OUTPUT_ORDER controls as shown in Figure 15(c).
3.8.4 Asynchronous Serial Outputs
Asynchronous channels must be output on a single
serial stream. Tag bits or separate frame strobes must be
used to identify the channels. In the asynchronous mode
each channel sample is output as a serial word (or complex
pair) as soon as the resampler has finished generating it. Tag
bits or separate frame strobes are used to match the serial
output word with the channel it came from. Asynchronous
channels must use NSERIAL=0, OUTPUT_ORDER=0, and
BLOCK_SIZE=0.
WORDS_PER_FRAME
and
FRAME_LENGTH must be set to 0 for real data and 1 for
complex data. Four bit tags are enabled by setting
TAG_EN=1 and TAG_22=0. The two bit tag mode
(TAGEN=0, TAG22=1) can be used to output 24 bit words
that are 22 bits of data plus 2 bits of tag.
Separate frame strobes are enabled by using the two bit
tag mode and setting the EN_4_FS control bit (address 28 of
© GRAYCHIP,INC.
- 20 -
August 27, 2001
This document contains information which may be changed at any time without notice