GC4016 Datasheet, PDF(22/83 Page) Texas Instruments

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GC4016 Datasheet, PDF (22/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

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GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

Table 3: Output Mode Controls

Suggested Default for Each Mode (hex values)

Control Register

Address

(Page 98)

Micro-

processor

mode

Wide Word

micro-

processor

mode

Serial modes

Four serial TDM output Asynchro-

outputs (synchronous) nous Mode

Tristate Controls

7F1

Output Formats

Output Modes

Output Frame Controls

282

073

Output Word Sizes

Output Clocks

Serial Mux Controls

Output Tag A

Output Tag B

Output Tag C

Output Tag D

Miscellaneous

034

NOTES: 1. For TDM serial or nibble modes the master chipâs value should be 7F, the slavesâ 7D.

2. For TDM serial or nibble modes the master chipâs value should be 28, the slavesâ 20.

3. For multi-chip modes the frame length is set as described in Section 3.8.3.

4. Also set the RND22control bit in address 19 (bit 6) of the resampler control page (page 64).

5. For Asynchronous parallel modes set address 20 to 28.

Nibble mode

7F1

Link mode

Parallel

mode

E85

reduce the interrupt rate and to let the user read more

samples after each interrupt.

When the user has finished reading the block of data he

sets the READY control bit in the Status Register (address1).

When the output FIFO has a new block of data ready, it will

clear the READY bit. If a block of data completes and the

READY bit is not set, then the chip sets the MISSED control

bit. The MISSED bit serves as a diagnostic indicating that the

processor was too slow and missed a block of data. Note that

the rate at which the blocks are filled, and therefore the rate

at which the data needs to be read from the microprocessor

port, is dependent upon how fast the resampler can generate

new output samples. When the resampler is interpolating,

which is the resamplerâs most commonly used mode, it will

generate multiple output samples each time it receives a

sample from a downconverter channel. The user should use

the resamplerâs clock divider to slow its computation rate if

the resampler is generating outputs too fast (See Section

3.5.4).

The RDY pin can serve as an interrupt to inform the

processor that a new block of samples is ready. The width

and polarity of the RDY pulse is programmable (See

EN_RDY in address16 and INV_RDY and RDY_WIDTH in

address 17).

The mapping of the output data into registers 16 through

31 is dependent upon the OUTPUT_ORDER control mode in

address 21, the number of active channels, and whether the

channels are synchronous or asynchronous.

If OUTPUT_ORDER=0 and BLOCK_SIZE=3, then each

block will contain the next four samples output from the

resampler. If the channels are synchronous, then the block

will contain one sample from each channel. If there are only

two active channels, then the block will contain two samples

from each channel. If there is only one active output channel,

then the block will contain four consecutive samples from the

active channel. If the channels are asynchronous, or if there

are three active channels, then the output block will contain

the next four samples computed by the resampler. In this

case tags are required to separate the channels.

OUTPUT_ORDER=0 must be used for asynchronous data.

If OUTPUT_ORDER=1 or 2, then the channels are

written into the FIFO using the channel number as part of the

address. In this mode the previous block is complete when

the Q-half of the output from channel A arrives. If the

resampler ratio is the same integral value for all channels,

then channels B, C and D can be powered down and back up

again while maintaining proper channel ordering. Channel A

may not be powered down because it provides the âBlock

Completeâ timing signal. OUTPUT_ORDER settings of 1 and

2 are valid for synchronous channels, but NOT for

asynchronous channels.

The following tables illustrate how the 24 bit channel

outputs are mapped into addresses 16 through 31 of pages

96 and 97. Note that addresses 16, 20, 24 and 28 are the

unused LSBs of the 32 bit words and always read back zero.

Addresses 19, 23, 27 and 31 contain the MSBs of the output.

In the 12,16, or 20 bit output mode, all values are rounded

into the MSBs and the unused LSBs are cleared. These

tables assume that BLOCK_SIZE = 3 which sets the block

size to four complex words.

- 17 -

August 27, 2001

This document contains information which may be changed at any time without notice

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