GC4016 Datasheet, PDF (27/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
EN_RDY=1 in the master chip, and set MASTER=0 and
EN_RDY=0 in the slave chips.
The SFS strobe behaves the same in the nibble mode
as in the serial mode except that the SFS strobe is coincident
with the first nibble in the word and that the SFS strobe can
not come every word in the real 16 bits per word mode
(REAL_ONLY=1, BITS_PER_WORD=0). The latter
exception means that for 16 bit real data, SFS_MODE must
be equal to 0 (one SFS strobe at the beginning of the frame)
AND the frame length cannot be one word
(FRAME_LENGTH can not equal 0). This restriction does not
apply to complex outputs or to 32 bit nibble output modes
The separate frame strobe mode described for
asynchronous serial data can also be used in the nibble
mode.
3.8.6 LINK Mode Output
The four serial output pins (P0, P1, P2 and P3) and the
serial clock (SCK) and RDY pins can be configured as a
nibble wide link port by setting OUTPUT_MODE=2,
NIBBLE=1 and LINK=1 in address 18. The link port can feed
an ADSP-2106x SHARC DSP chip’s link port. The P0, P1,
P2, P3 and SCK pins are in a tristate condition when the chip
powers up and need to be enabled by setting EN_SCK,
EN_P0, EN_P1, EN_P2 and EN_P3 in address 16. EN_RDY
must be low. In the LINK mode the RDY output pin becomes
the ACK (acknowledge) input pin which is tied to the link port
“LACK” signal. LACK is used to stall the output until the
processor is ready for it.
The outputs are transmitted in four bit nibbles on the
rising edge of SCK (INV_SCK in address 17 must be low). If
the ACK signal is low at the end of a 32 bit transfer, then the
clock will remain high and the transmission of the next word
will be delayed until ACK goes high again.
The link port transfers data as 32 bit packets. The user
can choose to transmit two 16 bit words per packet, or a
single 32 bit word. To transmit two 16 bit words per packet
the user must set BITS_PER_WORD to 0 and
WORDS_PER_FRAME to 1. To transmit a single 32 bit word
per packet the user must set BITS_PER_WORD to 1 and
WORDS_PER_FRAME to 0.
The link mode requires OUTPUT_ORDER, NSERIAL
and BLOCK_SIZE to be set to 0. FRAME_LENGTH and
SFS_MODE are unused and should also be set to 0. The link
mode clock rate is set by SCK_RATE.
If the outputs are synchronous, and the chip has been
initialized properly (see Section 3.12), then the first transfer
will be the I part of channel A followed by the Q part, followed
by the I/Q pairs from channels B, C and D. If the channels are
asynchronous, or initialization is not possible, then tag bits
must be used to identify the channel data. The tag bits for
synchronous data may be disabled once synchronization is
achieved.
The link mode normally puts the least significant bit in
P0. Note that this is opposite of the GC4014. For pin
compatibility with the GC4014 the control SMUX_0 in
address 22 should be set to 1. This will put the least
significant bit in P3.
When transferring two 16 bit words in a 32 bit link packet
the first word will end up in the upper 16 bits of the packet and
the second word in the lower 16 bits. This means that the
memory order in the DSP chip may end up being (QA, IA,
QB, IB, ...) for complex data and (I1, I0, I3, I2, ...) for single
channel real data. The REVERSE_IQ control bit in address
18 will eliminate this problem by swapping the I/Q pair (or the
I0/I1 pair) in the 32 bit packet.
3.8.7 Parallel Mode Output
The SCK, SFS, RDY and P0 through P23 pins are used
in the parallel mode to output 24 bit wide data samples. The
mode is enabled by setting the EN_SCK, EN_SFS,
EN_RDY, EN_P0, EN_P1, EN_P2, EN_P3 and EN_PAR bits
in address 16, and by setting OUTPUT_MODE=3,
MASTER=1, and PARALLEL=1 in address 18. The parallel
mode also requires NSERIAL=0 and OUTPUT_ORDER=0 in
address 21. FRAME_LENGTH is unused and should be set
to 0 in address 20.
The 24 bit samples are clocked out on the rising edge of
SCK (or the falling edge if INV_SCK is set). The SCK clock
is continuous and the SFS and RDY outputs are used to
identify when a valid sample has been clocked out. The data
valid flags will go high during the SCK clock period when the
24 bit sample is valid. The SFS and RDY flags behave in two
modes as controlled by the SFS_MODE control bits in
address 19.
If SFS_MODE is 0 or 1, then the SFS is IVALID and RDY
is QVALID. If the outputs are synchronous, and the chip has
been initialized properly (see Section 3.12), then the first
valid sample after initialization will be the I part of channel A.
The next valid sample will be the Q part, followed by the I/Q
pairs from channels B, C and D. If the channels are
asynchronous, or initialization is not possible, then tag bits
must be used to identify the channel data. The tag bits for
synchronous data may be disabled once synchronization is
achieved.
© GRAYCHIP,INC.
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August 27, 2001
This document contains information which may be changed at any time without notice