GC4016 Datasheet, PDF (36/83 Pages) Texas Instruments – MULTI-STANDARD QUAD DDC CHIP

GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
5.0 CONTROL REGISTERS
The chip is configured by writing to eight bit control registers. These registers are accessed for reading or writing using the
control bus pins (CE, RD, WR, A[0:4], and C[0:7]) described in Section 3.1. The 32 word address space is split into eight global
registers (addresses 0-7), eight unused registers (addresses 8-15) and 16 paged registers (addresses 16-31). The global
registers are available from each page. Address 2 is the page register which selects which control registers are accessed by
addresses 16 through 31.
5.1 GLOBAL CONTROLS
The eight global control registers are:
Table 11: Global Control Registers
ADDRESS
0
1
2
3
4
5
6
7
NAME
Global Reset
Status
Page
Checksum
General Syncs
Count Sync
Counter Byte 0
Counter Byte 1
DESCRIPTION
Miscellaneous general controls.
uP ready/missed, resampler overflows, checksum ready,
Page register for both 4 and 5 bit addressing modes
Checksum results register
Syncs for output, checksum. One shot.
Sync for counter, ramp selection
Ramp counter least significant byte.
Ramp counter most significant byte.
ADDRESS 0:
Global Reset, Powers up as 0xF0. Suggested Default is 0xF8 during configuration,
0x08 afterwards.
BIT
0 LSB
TYPE
R/W
NAME
CK_LOSS_DETECT
1
R/W
CK_2X_TEST
2
R/W
CK_2X_EN
3
R/W
EDGE_WRITE
4
R/W
RESAMPLER_RESET
5
R/W
PAD_RESET
6
R/W
OUT_BLK_RESET
7
R/W
GLOBAL_RESET
DESCRIPTION
Disable the clock loss detection circuitry. This circuitry protects the chip against
a current surge that may result if the clock is inactive for more than 100mS.
Setting this bit turns off the clock loss detection circuitry. Used for test, not
recommended for general use.
Test mode to output the doubled clock on SO. DVAL must be low. Normally set to
zero.
Changes the DVAL pin to become a CK_2X input pin. The chip normally uses
an internally generated doubled clock (twice the CK clock). Setting this bit allows
an externally generated doubled clock to be used. Used in test, not
recommended for general use.
Sets the edge write mode for the control interface. When low the data must be
stable while the write strobe is low. When high the outputs are latched on the
rising edge of the write strobe (WR | CE). A short (approximately 15 nS) write
recovery time is required during which time the chip should not be read from or
written to. Recommended to be set high.
This bit resets the resampler. This bit is set during power up and is cleared after
configuration.
Forces SFS and RDY pads to tristate during power up. The user needs to clear
this bit for proper operation of SFS and RDY.
This bit resets the output formatter block. This bit is set during power up and is
cleared after configuration.
This bit powers down the chip and tristates the output pins. This bit is set during
power up and is cleared after configuration.
© GRAYCHIP,INC.
- 31 -
August 27, 2001
This document contains information which may be changed at any time without notice