TL16C754 Datasheet, PDF (4/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
PN
FN
DESCRIPTION
RESET
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output
33
37
I and the receiver input will be disabled during reset time. See TL16C754 external reset conditions
for initialization details. RESET is an active high input.
RIA, RIB
RIC, RID
78, 24 8, 28
38, 64 42, 62
I
Ring indicator (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem has received a ringing signal from the telephone line.
A low to high transition on these input pins generates an modem status interrupt, if it is enabled.
RTSA, RTSB
RTSC, RTSD
Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.
7, 15 14, 22
47, 55 48, 56
O
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to 1. These pins only affects the transmit and receive
operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6,
for hardware flow control operation.
RXA, RXB
RXC, RXD
77, 25 7, 29
37, 65 41, 63
I
Receive data input. These inputs are associated with individual serial channel data to the 754A.
During the local loopback mode, these RX input pins are disabled and TX data is internally
connected to the UART RX input internally.
RXRDY
Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
34
38 O FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.
TXA, TXB
TXC, TXD
10, 12 17, 19
50, 52 51, 53
O
Transmit data. These outputs are associated with individual serial transmit channel data from the
754A. During the local loopback mode, the TX input pin is disabled and TX data is internally
connected to the UART RX input.
TXRDY
Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel
35
39 O FIFOs, TXRDY A–D. It goes low when there are a trigger level number of spares available. It goes
high when all four TX buffers are full.
VCC
6, 46, 13, 47,
66
64 ^{Pwr Power supply inputs}
XTAL1
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.
31
35
I
A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figures 10 and 11). Alternatively, an external clock can be connected to XTAL1 to provide custom
data rates.
XTAL2
32
36
O
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.
4
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