TL16C754 Datasheet, PDF (30/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
PRINCIPLES OF OPERATION
line control register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are
selected by writing the appropriate bits to the LCR. Table 10 shows line control register bit settings.
Table 10. Line Control Register (LCR) Bit Settings
BIT NO.
BIT SETTINGS
1:0 Specifies the word length to be transmitted or received.
00 – 5 bits
01 – 6 bits
10 – 7 bits
11 – 8 bits
2
Specifies the number of stop bits:
0 – 1 stop bits (Word length = 5, 6, 7, 8)
1 – 1.5 stop bits (Word length = 5)
1 – 2 stop bits (Word length = 6, 7, 8)
3
0 = No parity
1 = A parity bit is generated during transmission and the receiver checks for received parity.
4
0 = Odd parity is generated (if LCR(3) = 1)
1 = Even parity is generated (if LCR(3) = 1)
5
Selects the forced parity format (if LCR(3) = 1)
If LCR(5) = 1 and LCR(4) = 0 the parity bit is forced to 1 in the transmitted and received data.
If LCR(5) = 1 and LCR(4) = 1 the parity bit is forced to 0 in the transmitted and received data.
6
Break control bit.
0 = Normal operating condition
1 = Forces the transmitter output to go low to alert the communication terminal.
7
0 = Normal operating condition
1 = Divisor latch enable
line status register (LSR)
Table 11 shows line status register bit settings.
Table 11. Line Status Register (LSR) Bit Settings
BIT NO. BIT SETTINGS
0
0 = No data in the receive FIFO
1 = At least one character in the RX FIFO
1
0 = No overrun error
1 = Overrun error has occurred.
2
0 = No parity error in data being read from RX FIFO
1 = Parity error in data being read from RX FIFO
3
0 = No framing error in data being read from RX FIFO
1 = Framing error occurred in data being read from RX FIFO (i.e., received data did not have a valid stop bit)
4
0 = No break condition
1 = A break condition occurred and associated byte is 00. (i.e., RX was low for at least one character time frame).
5
0 = Transmit hold register is NOT empty
1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled.
6
0 = Transmitter hold AND shift registers are not empty.
1 = Transmitter hold AND shift registers are empty.
7
0 = Normal operation
1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. BIt 7 is cleared when no errors are
present in the FIFO.
30
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265