TL16C754 Datasheet, PDF (19/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
timing requirements T_A = –40°C to 85°C, V_CC = 3.3 V to 5 V ± 10% (unless otherwise noted)(see
Figures 9–16)
PARAMETER
TEST CONDITIONS
CP
Clock period
TRESET Reset pulse width
T3w
Oscillator/clock speed
VCC = 4.5 V
VCC = 3 V
T6s
Address setup time
T6h
Address hold time
T7d
IOR delay from chip select
T7w
IOR strobe width
T7h
Chip select hold time from IOR
T8d
Delay time between successive assertion of IOW and IOR
T8s
Setup time from IOW or IOR assertion to XTAL1 clock↑
T8h
Hold time from XTAL1 clock↓ to IOW or IOR release
T9d
Read cycle delay
T12d
Delay from IOR to data
VCC = 4.5 V
VCC = 3 V
T12h
Data disable time
T13d
T13w
IOW delay from chip select
IOW strobe width§
T13h
Chip select hold time from IOW
T15d
Write cycle delay
T16s
Data setup time
T16h
Data hold time
T17d
Delay from IOW to output
50 pF load
T18d
Delay to set interrupt from MODEM input
50 pF load
T19d
Delay to reset interrupt from IOR
50 pF load
T20d
Delay from stop to set interrupt
T21d
Delay from IOR to reset interrupt
50 pF load
T22d
Delay from stop to interrupt
T23d
Delay from initial IOW reset to transmit start
T24d
Delay from IOW to reset interrupt
T25d
Delay from stop to set RXRDY
T26d
Delay from IOR to reset RXRDY
T27d
Delay from IOW to set TXRDY
T28d
Delay from start to reset TXRDY
T30s
Address setup time
† _Baudrate
‡ _{P= Input clock period}
§ _{The IOW strobe width for the DLL and DLH accesses must be no more than two XTAL1 clock periods.}
LIMITS
MIN MAX
20
200
50
45
0
0
10
2P‡
0
4P‡
20
20
2P‡
30
47
15
10
2P‡
0
2P‡
16
15
50
70
70
1Rclk
70
100
8
24
70
1
1
70
16
10
UNIT
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
†
ns
ns
†
ns
Clk
µs
ns
†
ns
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