TL16C754 Datasheet, PDF (11/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
functional description (continued)
Table 4. Interrupt Control Functions
IIR[5–0]
000001
000110
001100
000100
000010
000000
010000
100000
PRIORITY
LEVEL
None
1
2
2
3
4
5
6
INTERRUPT
TYPE
None
Receiver line
status
RX timeout
RHR interrupt
THR interrupt
Modem status
Xoff interrupt
CTS, RTS
INTERRUPT SOURCE
INTERRUPT RESET METHOD
None
None
OE, FE, PE, or BI errors occur in characters in the FE< PE< BI: All erroneous characters are
RX FIFO
read from the RX FIFO. OE: Read LSR
Stale data in RX FIFO
Read RHR
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
Read RHR
TFE (THR empty)
Read IIR OR a write to the THR
(FIFO disable)
TX FIFO passes below trigger level (FIFO enable)
MSR[3:0]= 0
Read MSR
Receive Xoff character(s)/special character
Receive Xon character(s)/Read of IIR
RTS pin or CTS pin change state from active (low) Read IIR
to inactive (high)
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the
Rx FIFO. Reading the Rx FIFO updates LSR[4–2] to the appropriate status for the new character at the top of
the FIFO. If the Rx FIFO is empty, then LSR[4–2] is all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read
of the ISR.
interrupt mode operation
In interrupt mode (IER[3:0] = 0001), the processor is informed of the status of the receiver and transmitter by
an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see
if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.
Processor
IOW/IOR
INT
IER
1111
IIR
THR
RHR
Figure 5. Interrupt Mode Operation
polled mode operation
In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows polled
mode operation.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
11