TL16C754 Datasheet, PDF (25/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

IOW
(Write THR)
TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
SOUT
T
Figure 22. Error Case Timing Condition
workaround – 1
One workaround is to burst one or more additional bytes to the transmit FIFO within T1 after the first write. This
is the preferred method as the system throughput can be kept at maximum. Most applications also burst bytes
to the transmit FIFO and can easily write at least one byte within T1, as illustrated in Figure 23. For example,
at 19.2 baud, T1 exceeds 3 µs. which should be sufficient to load many bytes into the transmit FIFO. T1 is defined
as:
T1 = [(Divide-by factor^†) × (divisor in DLL, DLM)] × 2 × XTAL1 clock cycle period
† _{Divide-by-factor can be selected by either the CLKSEL tie-off during reset or changing MCR[7] after reset. Refer to CLKSEL terminal definition}
on page 3 of data sheet for detail description.
IOW
(Write THR)
SOUT
T1
Figure 23. Workaround Option 1 Timing
workaround – 2
Another workaround is to wait until T2 after the first write before writing subsequent bytes to transmit FIFO, as
illustrated in Figure 24. T2 is defined as:
T2 = [(Divide-by factor^†) × (divisor in DLL, DLM)] × 4 × XTAL1 clock cycle period
† _{Divide-by-factor can be selected by either the CLKSEL tie-off during reset or changing MCR[7] after reset. Refer to CLKSEL terminal definition}
on page 3 of data sheet for detail description.
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