TL16C754 Datasheet, PDF (31/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO
(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO
is output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
NOTE:
The error bits represented by LSR[4:2] are only valid when there is received data in the receive
FIFO, as indicated by LSR[0] being set. Software must be careful not to branch based on LSR[4:2]
when the receive FIFO is empty.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE:
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read
pointer is incremented by reading the RHR. Reading the RX FIFO when it is empty could cause
LSR[7] to be set, which can only be reset by clearing the RX FIFO via FCR[1]. It is stronly
recommended that the RX FIFO only be read when data is present.
modem control register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 12 shows modem control register bit settings.
Table 12. Modem Control Register (MCR) Bit Settings
BIT NO.
BIT SETTINGS
0
0 = Force DTR output to inactive (high)
1 = Force DTR output to active (low).
In loopback controls MSR[5].
1
0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low).
In loopback controls MSR[4].
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
2
0 Disables the FIFORdy register
1 Enable the FIFORdy register.
In loopback controls MSR[6].
3
0 = Forces the IRQ(A-D) outputs to high-impedance state
1 = Forces the IRQ(A-D) outputs to the active state.
In loopback controls MSR[7].
4
0 = Normal operating mode
1 = Enable local loopback mode (internal)
In this mode the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input internally.
5
0 = Disable Xon Any function
1 = Enable Xon Any function
6
0 = No action
1 = Enable access to the TCR and TLR registers.
7
0 = Divide by one clock input
1 = Divide by four clock input
This bit reflects the inverse of the CLKSEL pin value at the trailing edge of the RESET pulse.
NOTE: MCR[7:5] can only be modified when EFR[4] is set i.e., EFR[4] is a write enable.
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