TL16C754 Datasheet, PDF (28/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
PRINCIPLES OF OPERATION
register map (continued)
Table 8 lists and describes the TL16C754 internal registers.
Table 8. TL16C754 Internal Registers
Addr REGISTER BIT 7
BIT 6
000
RHR
bit 7
bit 6
000
THR
bit 7
bit 6
001
IER
0/CTS
0/RTS
interrupt
enable†
interrupt
enable†
010
FCR
Rx trigger Rx trigger
level
level
010
IIR
FCR(0)
FCR(0)
BIT 5
bit 5
bit 5
0/Xoff
interrupt
enable†
0/TX
trigger
level†
0/CTS,
RTS†
BIT 4
bit 4
bit 4
0/X Sleep
mode†
0/TX
trigger
level†
0/Xoff†
011
LCR
DLAB and Break Sets parity Parity type
EFR
control bit
select
enable
100
MCR
1x or
TCR and 0/Xon Any 0/Enable
4X clock
TLR
loopback
enable
101
LSR
0/Error in THR and
THR
Break
Rx FIFO
TSR
empty
interrupt
empty
110
MSR
CD
RI
DSR
CTS
111
SPR
bit 7
bit 6
bit 5
bit 4
BIT 3
bit 3
bit 3
Modem
status
interrupt
DMA
mode
select
Interrupt
priority
Bit 2
Parity
enable
IRQ
Enable
Framing
error
∆CD
bit 3
BIT 2
bit 2
bit 2
Rx line
status
interrupt
Resets
Tx FIFO
Interrupt
priority
Bit 1
No. of stop
bits
FIFOrdy
Enable
Parity
error
∆RI
bit 2
BIT 1
bit 1
bit 1
THR
empty
interrupt
Resets
Rx FIFO
Interrupt
priority
Bit 0
Word
length
RTS
Over-run
error
∆DSR
bit 1
BIT 0
bit 0
bit 0
Rx data
available
interrupt
Enables
FIFOs
Interrupt
status
Word
length
DTR
Data in
receiver
∆CTS
bit 0
000
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
001
DLH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
010
EFR
Auto-CTS Auto-RTS Special
Enable S/W flow S/W flow S/W flow S/W flow
character enhanced- control
detect functions†
Bit 3
control
Bit 2
control
Bit 1
control
Bit 0
100
Xon1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
101
Xon2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
110
Xoff1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
111
Xoff2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
110
TCR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
111
TLR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
111 FIFORdy RX FIFO RX FIFO RX FIFO RX FIFO TX FIFO TX FIFO TX FIFO TX FIFO
D status C status B status A status D status C status B status A status
† _{The shaded bits in the above table can only be modified if EFR[4] is enabled, i.e., if enhanced functions are enabled.}
READ/
WRITE
Read
Write
Read/
Write
Write
Read
Read/
Write
Read/
Write
Read
Read
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
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Write
Read/
Write
Read
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