TL16C754 Datasheet, PDF (14/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
functional description (continued)
programmable baud rate generator
The TL16C754 UART contains a programmable baud generator that takes the reference clock and divides it
by a divisor in the range between 1 and (2¹⁶–1). The output frequency of the baud rate generator is 16x the baud
rate. An additional divide-by-4 prescaler is also available and can be selected by the CLKSEL pin or MCR[7],
as shown in the following. The formula for the divisor is:
Divisor = (XTAL1 crystal input frequency / prescaler) / (desired baud rate × 16)
Where
+ _ȥȡȢ ⁺⁺ prescaler
1 when CLKSEL
4 when CLKSEL
high during reset, or MCR[7] is set to 0 after reset
low during reset, or MCR[7] is set to 1 after reset
Figure 9 shows the internal prescaler and baud rate generator circuitry.
XTAL1
XTAL2
Internal
Oscillator
Logic
Prescaler Logic
(Divide By 1)
Input Clock
Prescaler Logic
(Divide By 4)
MCR[7] = 0
Reference
Clock
Bandrate
Generator
Logic
MCR[7] = 1
Internal
Bandrate Clock
For Transmitter
and Receiver
Figure 9. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor.
If DLL and DLH are both zero, the UART is effectively disabled, as no baud clock will be generated.
The programmable baud rate generator is provided to select both the transmit and receive clock rates.
Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency 1.8432 MHz and
3.072 MHz, respectively.
14
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265