TL16C754 Datasheet, PDF (22/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
Start
Bit
Data Bits (5–8)
Stop
Bit
RX (A–D)
RXRDY (A–D)
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Next Data
Start Bit
T25d
Active
Data
Ready
T26d
Active
IOR
Figure 17. Receive Ready Timing in None FIFO Mode
RX (A–D)
RXRDY (A–D)
RXRDY
IOR
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
First Byte
That Reaches
The Trigger
Level
T25d
Active
Data
Ready
T26d
Active
Figure 18. Receive Timing in FIFO Mode
22
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265