TL16C754 Datasheet, PDF (3/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
Terminal Functions
TERMINAL
NAME
NO.
I/O
PN
FN
DESCRIPTION
A0
30
34
I Address bit 0 select. Internal registers address selection. Refer to Table 5 for Register Address Map.
A1
29
33
I Address bit 1 select. Internal registers address selection. Refer to Table 5 for Register Address Map
A2
28
32
I Address bit 2 select. Internal registers address selection. Refer to Table 5 for Register Address Map
CDA, CDB
CDC, CDD
79, 23 9, 27
Carrier detect (active low). These inputs are associated with individual UART channels A through
39, 63 43, 61 ^I D. A low on these pins indicates that a carrier has been detected by the modem for that channel.
CLKSEL
Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL selects
26
30
I the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET.
A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into
MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value.
CSA, CSB
CSC, CSD
9, 13, 16, 20,
49, 53 50, 54
I
Chip select A, B, C, and D (active low). These pins enable data transfers between the user CPU
and the TL16C754 for the channel(s) addressed. Individual UART sections (A, B, C, D) are
addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A through
CTSA, CTSB
CTSC, CTSD
4, 18 11, 25
44, 58 45, 59
I
D. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
754. Status can be checked by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7,
for hardware flow control operation.
D0–D2
D3–D7
68–70, 66–68,
71–75 1–5
I/O
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information
to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.
DSRA, DSRB 3, 19 10, 26
DSRC, DSRD 43, 59 44, 60
I
Data set ready (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.
DTRA, DTRB
DTRC, DTRD
5, 17 12, 24
45, 57 46, 58
Data terminal ready (active low). These outputs are associated with individual UART channels A
through D. A low on these pins indicates that the 754A is powered on and ready. These pins can
O be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to
low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a
reset.
GND
16, 36,
56, 76
6, 23,
40, 57
Pwr
Signal and power ground
INTA, INTB
INTC, INTD
Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA–D.
8, 14, 15, 21,
48, 54 49, 55
O
INTA–D are enabled when MCR bit 3 is set to a 1, interrupts are enabled in the interrupt enable
register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or when a modem status flag is detected.
INTA–D are in the high-impedance state after reset.
INTSEL
Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with MCR
bit 3 to enable or disable the 3-state interrupts INTA–D or override MCR bit 3 and force continuous
67
65
I interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving this pin low
allows MCR bit 3 to control the 3-state interrupt output. In this mode, MCR bit 3 is set to a 1 to enable
the 3-state outputs.
Read input (active low strobe). A valid low level on IOR will load the contents of an internal register
IOR
51
52
I defined by address bits A0–A2 onto the TL16C754 data bus (D0–D7) for access by an external
CPU.
IOW
11
18
I
Write input (active low strobe). A valid low level on IOW will transfer the contents of the data bus
(D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2.
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